Hi Bob,
Fig. 22.15 in your book (p. 525) ''A MOSFET feedback amplifier with 40-kHz open-loop bandwidth.'', it look seem you've used Miller Input Compensation technique. But compensation cap connect from Bot (neg. drv to output stage) to input.
This is different with your 50W MOSFET amplifier in 1984, the compensation cap from Top (pos. drv) and to input.
What's the different about result of both?!
Fig. 22.15 in your book (p. 525) ''A MOSFET feedback amplifier with 40-kHz open-loop bandwidth.'', it look seem you've used Miller Input Compensation technique. But compensation cap connect from Bot (neg. drv to output stage) to input.
This is different with your 50W MOSFET amplifier in 1984, the compensation cap from Top (pos. drv) and to input.
What's the different about result of both?!
Attachments
Hi Walkalone,
Whether the MIC is connected to the top or bottom of the bias spreader does not matter, since the bias spreader has no signal across it. However, note also that the resistors that determine the gain of the amplifier are connected to both the top and bottom of the bias spreader, somewhat decreasing DC offset.
Cheers,
bob
Hi Bob,
Hope you are enjoying your retirement.
I was wondering if you would like to like to comment on the Sansui diamond configuration, as used in the Sansui AU-X1 and others.
In particular is it a good topology, pitfalls, enhancements, the compensation method used etc. I have simulated the design somewhat and have posted the ltspice .asc file in another thread.
http://www.diyaudio.com/forums/soli...ifferential-pa-simulation-possible-build.html
I have heard that the amp has been known to oscillate, so I was wondering why that was so. I think it is the compensation, so I was wondering if you can confirm to change C11,12 to be a around 6pF or what ever else you determine. It actually helps the square wave response overshoot and the phase response, but the slew rate slows and the distortion goes up.
I see there is about 150 degrees of phase at 0dB which seems to be on the hairy edge in my mind? Is there a way to improve the phase?
I tried LSK389B and NXP BF862 jfets and they both seem to perform well as subs to the original 2sk129 pair.
I think if you have a good impression for this amp, I may do a layout/build for it and test it out.
If anything, it is fun learning a bit more about ltspice and figuring out why the designer made the choices that they did.
One last thing, have you posted a running list of errata, from your book, as I have found a few that I'd like to report, if they have not been discovered earlier.
Thx
Rick
Hope you are enjoying your retirement.
I was wondering if you would like to like to comment on the Sansui diamond configuration, as used in the Sansui AU-X1 and others.
In particular is it a good topology, pitfalls, enhancements, the compensation method used etc. I have simulated the design somewhat and have posted the ltspice .asc file in another thread.
http://www.diyaudio.com/forums/soli...ifferential-pa-simulation-possible-build.html
I have heard that the amp has been known to oscillate, so I was wondering why that was so. I think it is the compensation, so I was wondering if you can confirm to change C11,12 to be a around 6pF or what ever else you determine. It actually helps the square wave response overshoot and the phase response, but the slew rate slows and the distortion goes up.
I see there is about 150 degrees of phase at 0dB which seems to be on the hairy edge in my mind? Is there a way to improve the phase?
I tried LSK389B and NXP BF862 jfets and they both seem to perform well as subs to the original 2sk129 pair.
I think if you have a good impression for this amp, I may do a layout/build for it and test it out.
If anything, it is fun learning a bit more about ltspice and figuring out why the designer made the choices that they did.
One last thing, have you posted a running list of errata, from your book, as I have found a few that I'd like to report, if they have not been discovered earlier.
Thx
Rick
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Hi Rick,
This is an interesting amplifier. It is an example of a design where a unipolar JFET input stage is used in an amplifier with a push-pull VAS. I generally like such amplifiers, since I like JFET inputs and only good N channel duals are available. The key in such designs is how the output of the N-channel JFET pair is converted to signals that can drive the positive and negative VAS transistors.
In this design Sansui has effectively added another stage between the IPS and the VAS transistors. This contributes gain, but also phase lag.
It looks like each VAS transistor has a bit of Miller compensation around it, with rather small-value capacitors less than 5pF. I usually cringe at the use of such small-value capacitors. It also looks like a bit of Miller Input Compensation is used, again with uncomfortably small-value capacitors. Finally, it looks like there is a bit of shunt lag-lead compensation to stabilize the MIC loop.
Such a design may depend a lot on the characteristics of the transistors used. So substitutions and accurate models may be an issue. My overall impression is that this may be a design that is more complex than needed and one that may be cutting it too close on compensation.
Cheers,
Bob
I forgot to mention that I do not have a running list of errata for the book that I publish, but I am keeping track of those that people bring to my attention so that I can fix them in the Second Edition. I will appreciate any errata that you send me. I also like to be alerted to places where I have not done a clear enough job of explaining something.
Cheers,
Bob
Cheers,
Bob
Hi Bob,
Thanks for your feedback on the Sansui diamond design. So I take it that it is not your preferred topology, thus when looking at your book, you show Figure 7.13 which essentially does the same thing in another way(jfet diff pair & push-pull VAS). But it uses more small signal devices
than the Sansui design. I will sim, Figure 7.13, as well, just for the fun of it. Have you captured Figure 7.13 in LTspice? If so, you can save me some time if you post it.
I guess as a suggestion, do you think it is worth while to have a depository for each LTspice schematic of your designs/figures in the book. I have done a few of them, so I can contribute what I have for others to use.
I will also gather up the errata that I find in the book and post it at a later date.
I also extend my offer to do a pcb layout of one of the designs in the book, as I think it would be great for everyone to share a design and also play with a working design rather than just sim them up. Certainly would be a learning experience for me and others to take a sim'd design through to a working prototype.
Cheers
Rick
Thanks for your feedback on the Sansui diamond design. So I take it that it is not your preferred topology, thus when looking at your book, you show Figure 7.13 which essentially does the same thing in another way(jfet diff pair & push-pull VAS). But it uses more small signal devices
than the Sansui design. I will sim, Figure 7.13, as well, just for the fun of it. Have you captured Figure 7.13 in LTspice? If so, you can save me some time if you post it.I guess as a suggestion, do you think it is worth while to have a depository for each LTspice schematic of your designs/figures in the book. I have done a few of them, so I can contribute what I have for others to use.
I will also gather up the errata that I find in the book and post it at a later date.
I also extend my offer to do a pcb layout of one of the designs in the book, as I think it would be great for everyone to share a design and also play with a working design rather than just sim them up. Certainly would be a learning experience for me and others to take a sim'd design through to a working prototype.
Cheers
Rick
Hi Kindhornman,
Thanks for your very kind words. I have begun work on the Second Edition, but it has been slow-going for a number of reasons. I originally targeted September of this year, which would have made it four years between publication of the First and Second editions. Unfortunately, that is not going to happen. Realistically, I think best case is a year from now.
One thing that I am not good at is estimating the time it takes to do virtually anything. Plumbing is a good example. It usually takes me about 3X as long as I estimate.
Cheers,
Bob
Hi Bob,
Thanks for your feedback on the Sansui diamond design. So I take it that it is not your preferred topology, thus when looking at your book, you show Figure 7.13 which essentially does the same thing in another way(jfet diff pair & push-pull VAS). But it uses more small signal devices
I guess as a suggestion, do you think it is worth while to have a depository for each LTspice schematic of your designs/figures in the book. I have done a few of them, so I can contribute what I have for others to use.
I will also gather up the errata that I find in the book and post it at a later date.
I also extend my offer to do a pcb layout of one of the designs in the book, as I think it would be great for everyone to share a design and also play with a working design rather than just sim them up. Certainly would be a learning experience for me and others to take a sim'd design through to a working prototype.
Cheers
Rick
Hi Rick,
I did those simulations back in 2009. I'll see if I can find them. I did not organize the simulations in chapter folders as I should have
.I would be reluctant to post all of those simulations for numerous reasons, including the amount of work it would take. It would also mean making free access available to those who did not buy the book.
I don't have a problem with making something available on a small case-by-case basis if it is not too much trouble.
Cheers,
Bob
Hi Bob,
I sim'd Figure 7.13 today and got it going okay with a standard triple output as you are using in other figures. Seems to perform as well or better than the Sansui diamond design.
I understand your reasoning for not releasing or at least controlling who gets proprietary information (IP).
What is your policy with regard to me posting the .asc file as drawn in Figure 7.13 of your book, in this thread?
I sim'd Figure 7.13 today and got it going okay with a standard triple output as you are using in other figures. Seems to perform as well or better than the Sansui diamond design.
I understand your reasoning for not releasing or at least controlling who gets proprietary information (IP).
What is your policy with regard to me posting the .asc file as drawn in Figure 7.13 of your book, in this thread?
Me too, I remember project manager's asking for a time/task list when they were drawing up year long projects and entering the data into Microsoft project. So many un-known's or to TBD's.
Hi rsavas,
No problem at all. Thanks for asking. Glad you had luck with simulating the circuit.
BTW, many of the sims in my book were done before I came up with the Cordell models.
Cheers,
Bob
Hi Bob,
Okay, per you permission, I will post a working LTspice sim of Figure 7.13.
Now, if I was to design a pcb of this ckt, what are your conditions as far as releasing that to the general public? I mean offer a pcb, maybe the gerber/drill/fab data. I guess I would like to know the bounds of your IP? Something that could be stated up front in your book as well!
The figure 7.13 design, as I have captured it, has inherent around 7mV of DC offset (which in itself seems acceptable), but in reality, I am sure it is a lot more, due to component mis-matches, so to null it out, one needs either a servo or a pot to trim it out. Any suggestions to follow?
If possible, maybe you can comment on the baker clamp, bias spreader and any other enhancements/improvements to make this design something that can be a finished/working design.
I guess by your lack of response that you are not adverse to working with me on a real design, that could be offered to the DIY community at large? I take no offense, if you chose to work alone , keep it the way it is or work with someone else.
My aim is to prove to Doug Self and others that your work can/does represent real working designs. I understand that you do not need to prove anything, as you have done it over and over again, but I think myself and many others would like to have a working design to use and that you bless or endorse. I realize that there there are many designs to chose from, so that is a problem to sort out. If one can make the design as universal as possible, stuffing options, then at least that opens up the field. I do relaize that taking figure 7.13 and re-arranging it to be a standard lin design is not very possible, but to say use MOSFETs instead of bjt's for o/p's maybe a possibility.
So see attached the Ltspice ".asc" file of figure 7.13. I have posted my sim library previously in the Sansui thread to make it convenient.
Best regards
Rick
Okay, per you permission, I will post a working LTspice sim of Figure 7.13.
Now, if I was to design a pcb of this ckt, what are your conditions as far as releasing that to the general public? I mean offer a pcb, maybe the gerber/drill/fab data. I guess I would like to know the bounds of your IP? Something that could be stated up front in your book as well!
The figure 7.13 design, as I have captured it, has inherent around 7mV of DC offset (which in itself seems acceptable), but in reality, I am sure it is a lot more, due to component mis-matches, so to null it out, one needs either a servo or a pot to trim it out. Any suggestions to follow?
If possible, maybe you can comment on the baker clamp, bias spreader and any other enhancements/improvements to make this design something that can be a finished/working design.
I guess by your lack of response that you are not adverse to working with me on a real design, that could be offered to the DIY community at large? I take no offense, if you chose to work alone , keep it the way it is or work with someone else.
My aim is to prove to Doug Self and others that your work can/does represent real working designs. I understand that you do not need to prove anything, as you have done it over and over again, but I think myself and many others would like to have a working design to use and that you bless or endorse. I realize that there there are many designs to chose from, so that is a problem to sort out. If one can make the design as universal as possible, stuffing options, then at least that opens up the field. I do relaize that taking figure 7.13 and re-arranging it to be a standard lin design is not very possible, but to say use MOSFETs instead of bjt's for o/p's maybe a possibility.
So see attached the Ltspice ".asc" file of figure 7.13. I have posted my sim library previously in the Sansui thread to make it convenient.
Best regards
Rick
Hi Rick,
I have no problem with you making a PCB incorporating the circuit that is available to the general public for DIY use. I like the circuit and it would be flattering. As long as I get some credit for it and it works well, I'm happy.
I'm sure the circuit can be refined, of course. Moreover, a good complete amp takes more than just a good IPS/VAS.
Regarding the offset, I always recommend the use of a dc servo.
There is no need to convince Doug Self of anything, and those efforts are usually fruitless anyway
.I'll try to help by answering questions and offering advice here and there, but I often have trouble finding the time to get deeply involved.
Cheers,
Bob
Hi Bob,
Okay then, I will pursue this journey, but it may take a bit of time, as it is not the only project I am working on. It just gives me a break from other activities, like writing code for my stereo system project, that is now a few years old. Oh well, I have just entered retirement, so I have lots of time ahead of myself.
So the plan for me is to capture/layout in orcad. It will be mixed technology, small signal bjts/fets in SOT-23 and the power stuff in THole of course.
I will ask for a design/schematic & layout review, as a checking/sanity step.
May decide to start a new thread as well so that we can leave this thread for general discussion of book matters.
One last comment, since your book is about audio power amps, there is no way better to learn, than to take a design(paper) from concept to working prototype, then ready for mfg release. That involves many facet's of EE and ME.
Regards
Rick
Okay then, I will pursue this journey, but it may take a bit of time, as it is not the only project I am working on. It just gives me a break from other activities, like writing code for my stereo system project, that is now a few years old. Oh well, I have just entered retirement, so I have lots of time ahead of myself.
So the plan for me is to capture/layout in orcad. It will be mixed technology, small signal bjts/fets in SOT-23 and the power stuff in THole of course.
I will ask for a design/schematic & layout review, as a checking/sanity step.
Okay then feel free to comment on the circuit, I posted and tell me what should be refined. I believe it is a good place to start at?
May decide to start a new thread as well so that we can leave this thread for general discussion of book matters.
One last comment, since your book is about audio power amps, there is no way better to learn, than to take a design(paper) from concept to working prototype, then ready for mfg release. That involves many facet's of EE and ME.
Regards
Rick
LSk489 app note,figure 11, what spice model to use?
Anyone out there?
I read the Linear Systems app note on using the LSK489 = well done, lots to play with. I entered the design, figure 11 into LTspice and will post the schematic for others) to use and comment.
I added the input stage cascode, as an option, so that I could compare with LSK389 and BF862 jfets. It can be bypassed, when i find the correct lsk489 jfet model to use.
What spice model do I use for the LSK489?
I downloaded the set from the mfg web site and not sure exactly which one to use,JF201(_1),(_3),(_5),LS843(A),(B),(C)? I guess I could sim the models and compare to the data sheet, but I'll see what anyone else has to say.
Thx
Rick
Anyone out there?
I read the Linear Systems app note on using the LSK489 = well done, lots to play with. I entered the design, figure 11 into LTspice and will post the schematic for others) to use and comment.
I added the input stage cascode, as an option, so that I could compare with LSK389 and BF862 jfets. It can be bypassed, when i find the correct lsk489 jfet model to use.
What spice model do I use for the LSK489?
I downloaded the set from the mfg web site and not sure exactly which one to use,JF201(_1),(_3),(_5),LS843(A),(B),(C)? I guess I could sim the models and compare to the data sheet, but I'll see what anyone else has to say.
Thx
Rick
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Hi Rick,
The SPICE model for the LSK489 is the same as for the LS844. The LSK489 is essentially a lower-noise version of the LS844. Use the JF201 or the LS844 model on my site.
I'm going to be out of internet access for a week starting about now.
Cheers,
Bob
Hi Bob,
I tried the lsk844(0.12%@20K,4ohm load), model and compared it to the nxp bf862(0.016%@20K,4ohm load), the distortion is 10:1 favouring the bf862, I have no idea why, so Bob can you shed any light on this observation?
The lsk389c model gives 0.02%
This is with the cascode in the input diff amp!
Thx
Rick
I tried the lsk844(0.12%@20K,4ohm load), model and compared it to the nxp bf862(0.016%@20K,4ohm load), the distortion is 10:1 favouring the bf862, I have no idea why, so Bob can you shed any light on this observation?
The lsk389c model gives 0.02%
This is with the cascode in the input diff amp!
Thx
Rick
Hi Bob,
I tried the lsk844(0.12%@20K,4ohm load), model and compared it to the nxp bf862(0.016%@20K,4ohm load), the distortion is 10:1 favouring the bf862, I have no idea why. Bob can you shed any light on this observation?
The lsk389c model gives 0.02%
This is with the cascode in the input diff amp!
Thx
Rick
I tried the lsk844(0.12%@20K,4ohm load), model and compared it to the nxp bf862(0.016%@20K,4ohm load), the distortion is 10:1 favouring the bf862, I have no idea why. Bob can you shed any light on this observation?
The lsk389c model gives 0.02%
This is with the cascode in the input diff amp!
Thx
Rick
I'm in total agreement.
I would like to ask about your version of the HEC OPS.
You state "Q22 is mounted on the main heatsink for thermal feedback".
(below) is my simulation. (your Q22 is Q109 below)
Would not BOTH Q109/110 be used as thermal feedback ?
The other example of HEC (SYN08's) The output stage uses LFET's (negative coeff.)
and does not need this.
Another option would be to not use the HEC devices as such and
use a typical simple bias spreader at the OPS input.
Even as I have manipulated some currents/values , the below
simulation works as advertised. The HEC FB adjustments performed
just as your article said they would.
Fine tuning of Rhec (on schema) gave me .02% THD20 at high power.
...It's amazing how the most non-linear (IRFPxxx) of the 3 output device types (VFET/LFET/BJT) ,
can match or exceed a BJT EF3 OPS with this enhancement.
OS
