Bob Cordell's Power amplifier book

This in turn means that (with TPC) since the differential input voltage is reduced the input current will also be reduced for the same input voltage. This, I suspect, explains your observations, and does not in any way mean that the input impedance of the input stage has changed.

Lower AC input current at same input voltage means higher input Z ,
that it is due to lower differential voltage is just the other face
of a same coin.
 
...
Anyhow, I don't understand the rationales behind this FB network...
Hi Edmond

The rationale is that C2 and R3 balance with the output inductor and the speaker impedance.
So you need to include the output inductor and speaker impedance to model it properly.
Maybe not a brilliant rationale but I think it leaves C1 to provide a little lead.
But not that relevant because my concern was only whether it would be an EMI access path - and no one provided any actual data anyway.

Best wishes
David
 
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"I fail to appreciate how "TMC" increases the TIS input impedance: both "TMC" and TPC are shunt applied negative feedback schemes, so they both reduce TIS input impedance."

Correct.

Easily proven by considering the situation with simple MC. As Cdom impedance decreases with frequency, so does the input impedance to the TIS. And hence, due to the finite LTP current, the slew is limited to some clearly defined rate and the stage bandwidth as well. TPC/TMC cannot by the same token increase the TIS input impedance.
 
TPC increases loop gain across the audio band. This means that the error voltage driving the forward path of the amplifier is significantly reduced compared with "TMC" or, for that matter, simple single-pole Miller compensation.

This in turn means that (with TPC) since the differential input voltage is reduced the input current will also be reduced for the same input voltage. This, I suspect, explains your observations, and does not in any way mean that the input impedance of the input stage has changed.

This is correct, and is in line with the point that TPC can reduce input stage distortion while TMC does not.

Cheers,
Bob
 
I don't think TPC loads the TIS to any significant degree compared with "TMC", especially if the larger of the two capacitors is connected to the input of the TIS. Note that there is no such thing as "VAS" in the topology under discussion.

This is the only explanation I can think of as Ive spent a couple of hours simulating and always TMC give the best results. :eek:
 
Hi keantoken,

This is a good point, but I have not yet had time to fully absorb the other post. An ordinary 2-transistor current mirror nominally puts only one Vbe of Vce on the transistor since the base and collector of one transistor are connected together. I'm assuming that this is the low Vce condition you are referring to. If we get into quasi-saturation with this diode-connected transistor it can certainly cause degradation. This of course will depend on the current flowing and the type of transistor.

I usually use the "helpered" current mirror that is popular in integrated circuits, where an emitter follower is added to supply the base current of the two mirror transistors. This adds an extra Vbe of headroom to the transistor that is normally diode connected. I discuss this current mirror in Chapter 2 on page 35, Figure 2.9b. If this current mirror is used with a Darlington VAS, then both transistors of the current mirror see approximately the same 2Vbe Vce (not counting emitter degeneration drop). Does this address your point, or am I missing something?

Cheers,
Bob

The problem I see is not in mirror balance, but output impedance. In the quasi-saturation region, collector impedance can be 500R for some transistors, notably japanese high-voltage types that people think will work well here. The 500R shunts the input of the common-emitter stage (VAS - ha!). Furthermore, if the CE is degenerated significantly, Vce can vary widely and this will modulate collector impedance in and out of the quasi-sat region, causing distortion.

The balance is another issue.
 
There is really no reason to worry yourself about the input impedance at the transistor's base

Actually there is. It's not common but certain source impedances can cause an amp to oscillate. This occurs at RF where the base impedance dominates over the resistor impedance. It is usually the result of zealous experimentation with compensation methods, and/or not enough input decoupling (shunt capacitance).
 
I don't think TPC loads the TIS to any significant degree compared with "TMC", especially if the larger of the two capacitors is connected to the input of the TIS. Note that there is no such thing as "VAS" in the topology under discussion.

Sometimes TPC can be the dominant load on the CE stage, in amps with very heavily buffered output stages. Such an amp probably already has low distortion, but the point is that loading of TPC is now a significant distortion mechanism. Another closely related distortion mechanism is the voltage distortion at the CE output, which enters the signal path only because it is conducted by the impedance of the CE output node, which in this case is dominated again by TPC.

Because TMC does not load the CE output or the CE itself, it can work better than TPC in amps with heavily buffered output stages and very linear input stages.
 
Actually there is. It's not common but certain source impedances can cause an amp to oscillate. This occurs at RF where the base impedance dominates over the resistor impedance. It is usually the result of zealous experimentation with compensation methods, and/or not enough input decoupling (shunt capacitance).

I fail to appreciate how the base input impedance can dominate that provided by the resistor to ground under any circumstances.
 
I fail to appreciate how the base input impedance can dominate that provided by the resistor to ground under any circumstances.
The last amp schematic shown in this thread had "base input impedance" = 120 Ohms * current gain of input device * Loop gain of the global feedback network. Current gain drops at HF. Loop gain drops at HF. During clipping, there is no loop gain. So under certain circumstances it's significant.

To see Keantoken's point about certain source impedances causing oscillation, it's useful to look at it from a different point of view:
With an LTP input stage, the transconductance = 1 / (2*Re + 2*RE + Rsrc / current gain)

The higher the source impedance, the more significant that last term becomes. At high frequencies the current gain drops, causing the transconductance to drop. This adds an extra pole to the amp's open loop gain, and thus also to the loop gain, which might make it unstable.

Having an RF filter at the input helps in this regard as the capacitor to ground provides a low impedance path at RF. It's still a good idea to check stability with the input open circuit as well as shorted, IMO.
 
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Here a real world example of Bob's "Bridged TPC" merged with Douglas's "Blameless":

http://www.diyaudio.com/forums/soli...ormance-class-ab-power-amp-200w8r-400w4r.html

Many thx to Bob Cordell and Douglas Self for their excellent books.

Best regards,
Toni

Hi Tony,

It looks like you have done a great job here!

Interesting that you got lower THD in the real world than in the SPICE simulations; very good performance, indeed.

If I read the schematic right, you are using only a double EF output stage, not a Triple. It is impressive that you got that performance with only a double.

Nice pix, also.

I hope people here will follow your link and see the post.

Cheers,
Bob
 
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Dear Bob,

thank you. Have had the best teachers man can have! ;)
I feel really honored due to your personal response.

The better real world THD performance may be influenced by

  • the usage of TTC5200/TTA1943 which have lower Cob (145p/240p) as 2SC5200/2SA1943 (200p/360p) or
  • SPICE models of the output stage BJT's are not very good
  • THD Analyzer has had bandwidth limit 80 kHz switched on (can we simulate this with LTSpice?
  • all parts are hand selected and matched where it makes sence
  • PCB is 70µ and designed thinking about HF requirements (GND Plane)
Needs some time to find the reason why.


Your "bridged TPC" example pushed the THD20 performance! The values in the schematic where determined on a trial and error basis - good old square wave on input and bread board feeling ...
Afterwards I put the values into SPICE simulation to learn loop gain analysis ...


Maybe it's an accident that the 2 stage EF works? :cool:


  • doubled the VAS current to get out more mA to drive the first EF stage (started with 3EF and measured VAS load; calculated the higher base current to drive the paired first EF bjt's)
  • paired the first EF stage to keep them cool and to be able to provide enough mA's for power BJT's driving 3R load
  • searched for high beta types for power BJT's
So - time to go to bed now!
Best regards and Greetings from Tyrol,


Toni



P.S.: Also I have tried TMC variants, but got the amp either not stable or stable but with bad performance compared to B-TPC



P.P.S.: Keep on going to write such excellent books for us!
 
Dear Bob,

thank you. Have had the best teachers man can have! ;)
I feel really honored due to your personal response.

The better real world THD performance may be influenced by

  • the usage of TTC5200/TTA1943 which have lower Cob (145p/240p) as 2SC5200/2SA1943 (200p/360p) or
  • SPICE models of the output stage BJT's are not very good
  • THD Analyzer has had bandwidth limit 80 kHz switched on (can we simulate this with LTSpice?
  • all parts are hand selected and matched where it makes sence
  • PCB is 70µ and designed thinking about HF requirements (GND Plane)
Needs some time to find the reason why.


Your "bridged TPC" example pushed the THD20 performance! The values in the schematic where determined on a trial and error basis - good old square wave on input and bread board feeling ...
Afterwards I put the values into SPICE simulation to learn loop gain analysis ...


Maybe it's an accident that the 2 stage EF works? :cool:


  • doubled the VAS current to get out more mA to drive the first EF stage (started with 3EF and measured VAS load; calculated the higher base current to drive the paired first EF bjt's)
  • paired the first EF stage to keep them cool and to be able to provide enough mA's for power BJT's driving 3R load
  • searched for high beta types for power BJT's
So - time to go to bed now!
Best regards and Greetings from Tyrol,


Toni



P.S.: Also I have tried TMC variants, but got the amp either not stable or stable but with bad performance compared to B-TPC



P.P.S.: Keep on going to write such excellent books for us!

Thanks for your very kind words, astx. I'm very happy if I have played a small role in your success and excellent design.

It's clear that you have paid a lot of attention to detail, thought things out, and tried different ideas. On top of that, you measured and listened.

I'm glad that Bridged TPC worked well for you. I'll try to do a better job in the future writing about TPC and TMC, with more material and better design guidelines.

Cheers,
Bob
 
Common Emitter OPS with floating supplies.

Mr. Cordell, Prof. Cherry in his Electronic World july 1997 article describes (Fig 1d) a topology with Common Emitter OPS and floating power supplies. This has many similarities (?!) with the highly developed Lin topology which is the basis of most PA stuff (ie we can use most of our present pontificating) .. but also many advantages to offset the extra supplies.

John Vanderkooy describes such a beast at A Simple Reliable Power Amplifier with Minimal Component Count

IMHO, this is far more deserving of your attention than even footling differences between 'pure Cherry' and evil TMC :)

I sincerely hope you will be able to do 'real life' work on this before your next edition.