Hello,
Yesterday i removed the top plate because i received the transformer from Hammond to make the supply for the lifepo4 board.. There is an Ll2733 that can be removed now being used in the LCLCLC supply for the 12 volt. One them just installed to get a bit more voltage drop! There is the wave IO board and two tiny chokes used to offer a cleaner voltage to the 3,3 V regulators on the mainboard. Removing this elements will allow me to move all the parts( now on top of the chassis) inside and CLOSE to the mainboard.
It will require some patience and brainstorming but once this two or three level " construction " is done everything now pictured outside can be moved outside ( moving to the backside of the chassis, after removing the backplate which doesnt hold a single part and of course after removing the 4 bolts that are used to fix the construction to the bars that are located in the top of the chassis)
After interconnecting all the boards in the construction. There will be two RG400 cables going to the clocks from Andrea, the DC input for the lifepo4 that will come from a supply made by Doede which will be inside the chassis and the I2S cables going to the DDDAC. These 3 connections will be accessible by removing bottom, top and blackplate because none of these are used for mounting anything regarding electronics.
Greetings,Eduard
Yesterday i removed the top plate because i received the transformer from Hammond to make the supply for the lifepo4 board.. There is an Ll2733 that can be removed now being used in the LCLCLC supply for the 12 volt. One them just installed to get a bit more voltage drop! There is the wave IO board and two tiny chokes used to offer a cleaner voltage to the 3,3 V regulators on the mainboard. Removing this elements will allow me to move all the parts( now on top of the chassis) inside and CLOSE to the mainboard.
It will require some patience and brainstorming but once this two or three level " construction " is done everything now pictured outside can be moved outside ( moving to the backside of the chassis, after removing the backplate which doesnt hold a single part and of course after removing the 4 bolts that are used to fix the construction to the bars that are located in the top of the chassis)
After interconnecting all the boards in the construction. There will be two RG400 cables going to the clocks from Andrea, the DC input for the lifepo4 that will come from a supply made by Doede which will be inside the chassis and the I2S cables going to the DDDAC. These 3 connections will be accessible by removing bottom, top and blackplate because none of these are used for mounting anything regarding electronics.
Greetings,Eduard
Attachments
smooth dancer
I had a similar problem. I regret to report that I never definitively figured out what caused it or how I fixed it. The system worked. I popped in reclockpi and same thing... now no sound. In my case I had well worn U.FL cables so I thought that must be it. I replaced the U.FL cables but one set were 6" long. Ultimately I got it to work with the new cables, but only by deleting I2StoPCM. At best I could only get that to work with massive distortion. My guess after numerous attempts is that somehow reclockpi is more sensitive to connection of the I2S output. That it needs a really good mclk U.FL and really good output cables that are not too long. I wish I had a scope to debug things like this. But based on my experience I would say focus on the mclk and I2S out connections and length. I also suggest you remove it and reconfirm that the system works without, then reinstall. And make sure the connections of your I2S output are really good. Assume that reclockpi outputs a weaker output signal and you may find the issue. I can add that I use FIFOPi Q1. I also wonder if FIFOPi Q3 outputs a stronger signal than the earlier versions that somehow makes it through reclockpi. At one point I was convinced I needed to replace FIFO with Q3, but it seems like an expensive experiment and I hate throwing new parts at this thing like a needle in a haystack. The sound is very good once you get it going so it's worth the frustration.
I had a similar problem. I regret to report that I never definitively figured out what caused it or how I fixed it. The system worked. I popped in reclockpi and same thing... now no sound. In my case I had well worn U.FL cables so I thought that must be it. I replaced the U.FL cables but one set were 6" long. Ultimately I got it to work with the new cables, but only by deleting I2StoPCM. At best I could only get that to work with massive distortion. My guess after numerous attempts is that somehow reclockpi is more sensitive to connection of the I2S output. That it needs a really good mclk U.FL and really good output cables that are not too long. I wish I had a scope to debug things like this. But based on my experience I would say focus on the mclk and I2S out connections and length. I also suggest you remove it and reconfirm that the system works without, then reinstall. And make sure the connections of your I2S output are really good. Assume that reclockpi outputs a weaker output signal and you may find the issue. I can add that I use FIFOPi Q1. I also wonder if FIFOPi Q3 outputs a stronger signal than the earlier versions that somehow makes it through reclockpi. At one point I was convinced I needed to replace FIFO with Q3, but it seems like an expensive experiment and I hate throwing new parts at this thing like a needle in a haystack. The sound is very good once you get it going so it's worth the frustration.
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Hello,
I already ordered some UFL cables. On the Fifopi board there is a UFL connector . On the DDDAC mainboard i will just have to connect the 3 central conductor and leave the screen floating.
Also connected the shield at the 10 pin connector ground side… do not let it float Ed
These are paste and copy about UFL connection.
I think i already wrote it before that to me it is strange to use UFL chassis part and plug on the Fifopi side that will '' create '' a 50 ohm impedance and on the DDDAC mainboard side you will just use the central conductor and connect in a very '' basic way '' I dont think here there is a 50 ohm impedance.
The screens of all 3 UFL tiny cables should be connected to the GND as illustrated on the left bottom side of the screen.
Greetings, Eduard.
P.s because you can read many times that I2S cable should be short and equal length i could well imagine that once they get a little bit to long they could '' stop working properly ''
I already ordered some UFL cables. On the Fifopi board there is a UFL connector . On the DDDAC mainboard i will just have to connect the 3 central conductor and leave the screen floating.
Also connected the shield at the 10 pin connector ground side… do not let it float Ed
These are paste and copy about UFL connection.
I think i already wrote it before that to me it is strange to use UFL chassis part and plug on the Fifopi side that will '' create '' a 50 ohm impedance and on the DDDAC mainboard side you will just use the central conductor and connect in a very '' basic way '' I dont think here there is a 50 ohm impedance.
The screens of all 3 UFL tiny cables should be connected to the GND as illustrated on the left bottom side of the screen.
Greetings, Eduard.
P.s because you can read many times that I2S cable should be short and equal length i could well imagine that once they get a little bit to long they could '' stop working properly ''
Attachments
that is by design Ed. If the DDDAC would have a 50 Ohm input and the logic is 5 Volt, there would be a 100mA current needed. No typical logic driver will do that without collapsing (20mA is more typical as maximum)
But there is more. Assuming the source would have exactly 50 Ohm impedance to drive the UFL cable AND the input would be 50 Ohm at the DDDAC Side, you would end up with half the voltage i.e. 2,5 or 1,65 Volt logic,
that would not work. This whole 50 Ohm thing is for analog HF signal and test and measurement setups to avoid excessive noise (scopes etc). Not for digital logic circuits...
Hello Doede,
If you say so it will be right. lol
So connect each screen from the UFL cable with its own wire to the GND terminal.
Do you have a real life picture which are the 4 soldering '' spots '' that i need to use. Will probably to enter the cable through the mainboard because the UFL terminals on the fifopi will be located close to the center of mainboard on the soldering side.
Greetings, Eduard
If you say so it will be right. lol
So connect each screen from the UFL cable with its own wire to the GND terminal.
Do you have a real life picture which are the 4 soldering '' spots '' that i need to use. Will probably to enter the cable through the mainboard because the UFL terminals on the fifopi will be located close to the center of mainboard on the soldering side.
Greetings, Eduard
All FifoPi and ReClockPi outputs are 50 ohm series source impedance terminated. So, no need the end termination resistors.
Ian
I can measure later. I think it may seem strange, but change of standoffs was the only thing i did. The pins on gpio is very long and one should think that as long as the pins going almost all the way in, it will be ok.
Edit; maybe there was a bad connection somewhere else, and after turning around and checking the boards and wiring, this was enough to solve the problem.
Edit; maybe there was a bad connection somewhere else, and after turning around and checking the boards and wiring, this was enough to solve the problem.
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Hello,
Because there are different lengths of stand off when you buy the complete collection of prints it could well be that if you use the ones that need to be used to attach a circuit to the chassis instead of the ones needed between circuit boards you can already get a less '' safe '' connection. If i look at the raspberry connection to the station pi board you can just say a tiny bit( 1,5 mm max) of the pins inside the terminal.
I havent looked at Ian's original photos to see if that bit of clearance is there as well.
One more time being proven that a good connection is the easiest way to avoid problems.
Greetings. Eduard
Because there are different lengths of stand off when you buy the complete collection of prints it could well be that if you use the ones that need to be used to attach a circuit to the chassis instead of the ones needed between circuit boards you can already get a less '' safe '' connection. If i look at the raspberry connection to the station pi board you can just say a tiny bit( 1,5 mm max) of the pins inside the terminal.
I havent looked at Ian's original photos to see if that bit of clearance is there as well.
One more time being proven that a good connection is the easiest way to avoid problems.
Greetings. Eduard
Trying to get the most out of TWTMC clocks for FifoPi system (4)
STS sine to square converter board signal quality measurement
DACs take the clocks in square waves, not in sine waves. So the sine to square wave converter is also very significant. DACs are a kind of digital logic. Clock Jitter for a DAC is decided by the edges of the clocks, not the phase of the sine wave. The DAC performance can be degraded if the quality of the square wave is not good enough, even if it is already with very good close-in phase noise.
I had big hopes for TWTMC-DIRXO with SC-cut crystal because the sine wave phase noise measurement results were very good. However the square wave jitter measurement result was not as good as I expected. So I did more tests to the STS square wave outputs in the time domain. Please find the waveform results attached. Left is STS output waveform, and the right is the CCHD957 output as reference.
Testing conditions were:
LC584AXL 1GHz Oscilloscope with jitter measurement package
Time base 10ns/div
Run at 8 GS/s sampling with 1GHz bandwidth fully opened
50 ohm terminated coaxial cable input
TWTMC-DIRXO power supply: 13.2V LifePO4
TWTMC-STS and CCHD957 power supply: pure 3000F ultracapacitor precharged to 3.3V (could be the best PSU in the real world)
Frequency 22.5792 MHz
I saw issues on the STS output:
1. DIRXO+STS has big overshoot and ringing at both rising and falling edges. CCHD957 output looks much better
2. Rising and falling time were around 1.4ns. Under the same condition CCHD957 was just 0.6ns
3. Noise and ripples can be seen at both high and low logic levels. CCHD957 logic levels are more clean.
4. DIRXO +STS frequency was 22.5774MHz, while CCHD957 was 22.5789 MHz (more closed to 22.7592MHz with higher accuracy)
These issues could result in:
1. Overshoot and ringing is a kind of AM noise which can be coupled into the power supply thus modulating the FM phase noise.
2. Slower clock rising and falling edges will introduce more noise into time jitter
3. Noise over logic levels can be transferred into DAC through both GND and signal.
So I sent an email to Andrea again asking for help. His answers were:
1. STS is good enough. It was measured with perfect phase noise by Timepod
2. The waveform shape does not affect the phase noise or the jitter performance since they are measured at zero crossing
3. raising/falling time does not matter, the only important thing is that the transaction happened always at the same time interval
4. absolute frequency and long term stability (Allan deviation) don't matter in digital audio
While...I don’t think all his points are reasonable. If waveform shape doesn’t affect the jitter performance, why don’t we use the sine wave directly for a DAC? Actually besides the close-in phase noise, time domain clock signal quality can also affect the jitter of the DAC internal clocks and then the final sound quality. The improvements made by ReClockPi could be a good example. Now I think I know the reason why Andrea can not measure STS issues in phase domain by his Timepod.
Please find the third picture attached. Basically any square wave contains components of both fundamental frequency and infinite harmonic frequencies. There are two square waves in the picture. DAC will see the two square waves in totally different quality levels. However, using a phase noise analyzer such as a Timepod, the close-in phase noise measurement results will be exactly the same. The reason is that the Timepod can only see the fundamental frequency component (which is cos(wt) in the picture) due to the limitation of bandwidth (30MHz for Timepod). That means it can not tell what’s the quality of a square wave except the close-in phase noise of the fundamental frequency.
This test is very easy. Everybody can duplicate this test. But please use a 1GHz or higher digital oscilloscopes. Otherwise waveform details will be missing.
What I’m looking for is a way of improvement. But Andrea told me that he doesn’t have any solutions so far.
In this case I’m afraid I have to design a sine to square wave converter board for my FifoPi to adapt TWTMC sine clocks by myself. I’ll see if I can make any improvement and get better results.
Ian
Other links
(1). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-657.html#post6668751
(2). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-660.html#post6671042
(3). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-662.html#post6675622
STS sine to square converter board signal quality measurement
DACs take the clocks in square waves, not in sine waves. So the sine to square wave converter is also very significant. DACs are a kind of digital logic. Clock Jitter for a DAC is decided by the edges of the clocks, not the phase of the sine wave. The DAC performance can be degraded if the quality of the square wave is not good enough, even if it is already with very good close-in phase noise.
I had big hopes for TWTMC-DIRXO with SC-cut crystal because the sine wave phase noise measurement results were very good. However the square wave jitter measurement result was not as good as I expected. So I did more tests to the STS square wave outputs in the time domain. Please find the waveform results attached. Left is STS output waveform, and the right is the CCHD957 output as reference.
Testing conditions were:
LC584AXL 1GHz Oscilloscope with jitter measurement package
Time base 10ns/div
Run at 8 GS/s sampling with 1GHz bandwidth fully opened
50 ohm terminated coaxial cable input
TWTMC-DIRXO power supply: 13.2V LifePO4
TWTMC-STS and CCHD957 power supply: pure 3000F ultracapacitor precharged to 3.3V (could be the best PSU in the real world)
Frequency 22.5792 MHz
I saw issues on the STS output:
1. DIRXO+STS has big overshoot and ringing at both rising and falling edges. CCHD957 output looks much better
2. Rising and falling time were around 1.4ns. Under the same condition CCHD957 was just 0.6ns
3. Noise and ripples can be seen at both high and low logic levels. CCHD957 logic levels are more clean.
4. DIRXO +STS frequency was 22.5774MHz, while CCHD957 was 22.5789 MHz (more closed to 22.7592MHz with higher accuracy)
These issues could result in:
1. Overshoot and ringing is a kind of AM noise which can be coupled into the power supply thus modulating the FM phase noise.
2. Slower clock rising and falling edges will introduce more noise into time jitter
3. Noise over logic levels can be transferred into DAC through both GND and signal.
So I sent an email to Andrea again asking for help. His answers were:
1. STS is good enough. It was measured with perfect phase noise by Timepod
2. The waveform shape does not affect the phase noise or the jitter performance since they are measured at zero crossing
3. raising/falling time does not matter, the only important thing is that the transaction happened always at the same time interval
4. absolute frequency and long term stability (Allan deviation) don't matter in digital audio
While...I don’t think all his points are reasonable. If waveform shape doesn’t affect the jitter performance, why don’t we use the sine wave directly for a DAC? Actually besides the close-in phase noise, time domain clock signal quality can also affect the jitter of the DAC internal clocks and then the final sound quality. The improvements made by ReClockPi could be a good example. Now I think I know the reason why Andrea can not measure STS issues in phase domain by his Timepod.
Please find the third picture attached. Basically any square wave contains components of both fundamental frequency and infinite harmonic frequencies. There are two square waves in the picture. DAC will see the two square waves in totally different quality levels. However, using a phase noise analyzer such as a Timepod, the close-in phase noise measurement results will be exactly the same. The reason is that the Timepod can only see the fundamental frequency component (which is cos(wt) in the picture) due to the limitation of bandwidth (30MHz for Timepod). That means it can not tell what’s the quality of a square wave except the close-in phase noise of the fundamental frequency.
This test is very easy. Everybody can duplicate this test. But please use a 1GHz or higher digital oscilloscopes. Otherwise waveform details will be missing.
What I’m looking for is a way of improvement. But Andrea told me that he doesn’t have any solutions so far.
In this case I’m afraid I have to design a sine to square wave converter board for my FifoPi to adapt TWTMC sine clocks by myself. I’ll see if I can make any improvement and get better results.
Ian
Other links
(1). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-657.html#post6668751
(2). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-660.html#post6671042
(3). https://www.diyaudio.com/forums/dig...mate-weapon-fight-jitter-662.html#post6675622
Attachments
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Sounds good. FWIW, a couple of suggestions should you make this available to your base.
1. Use all six pins to install it. We all are having issues with RG400 cable displacing the little squarer pcb from FIFOPi. 6 pins might make a stronger connection.
2. provide a working sense pin to enable FIFO to turn off the squarer. FIFOPi versions prior to Q3 can only run one clock that does not support the sense pin. It would be appreciated by many of your earlier FIFO customers to be able to run 2 clocks.
I think some people would buy your version of the squarer if you show it has a sound improvement. More would buy it just to get the two features I mentioned with the sound being a bonus.
