Hi TT,
bipolar and mosfet cascode has been known for almost 20 years in SMPS business. It was mainly used when there was lack of 500V mosfets with decent Rdson. While it does produce respectable switching times around 10ns, you still have to account for bipolar stored base charge (which is dependant on collector current) and resulting turn off delay in the range of 100ns. Last article i saw promoting this technology was from several years ago and they only managed 500kHz switching frequency. If you are interested, I can find the article and scan photos of really ugly switching vaweforms with tons of ringing it produced. At high speed switching, leakage inductance is your worst enemy, not Miller capacitance.
Best regards,
Jaka Racman
bipolar and mosfet cascode has been known for almost 20 years in SMPS business. It was mainly used when there was lack of 500V mosfets with decent Rdson. While it does produce respectable switching times around 10ns, you still have to account for bipolar stored base charge (which is dependant on collector current) and resulting turn off delay in the range of 100ns. Last article i saw promoting this technology was from several years ago and they only managed 500kHz switching frequency. If you are interested, I can find the article and scan photos of really ugly switching vaweforms with tons of ringing it produced. At high speed switching, leakage inductance is your worst enemy, not Miller capacitance.
Best regards,
Jaka Racman
Hi TT,
I’m afraid I can’t release any of the FPGA prototypes, as I do not own the IP. Anyhow, none of the FPGA’s performed as well as the TI or Sony.
For performance results of the Sony / TI / Zetex see my earlier postings in this thread.
The latest Renesas M65818AFP (Ex Mitsubishi - does anybody know if this is the Sony CXD9730?) now has a 1.4MHz (32fs) PWM output mode; I guess this is really only for the “Headphone” mode where Sony suggests to integrate the outputs directly. I speculate that Sony added this mode to reduce the high background noise everybody seems to complain about – not a good thing when you’re listening though headphones. If there is a background hiss problem with Sony products, then the fault lays with the surround circuits, and not their modulator design - as I measured a DR of over 116dB. There’s a new control register to allow summing of the output phases to increase drive current for the headphone circuit.
There’s also three extra modulation formats.
Reading between the lines of the bad “Japanese English” I believe there’s AD, BD and 2 other modes (forms 3 & 4) I don’t fully understand, maybe an inter-channel Phase shifted variant to reduce the net RF emissions of the output stages? The older Sony CXD9634Q / M65817AFP only had 16fs PWM rate (768KHz) and AD modulation.
An interesting limitation with Sony’s BD modulation (Mode 2) is that it will only operate if the Noise Shaper is set to 5Bits, and @ 768KHz. Having to reduce the Noise Shaper to 5Bits seems a major limitation.
I’m afraid I can’t release any of the FPGA prototypes, as I do not own the IP. Anyhow, none of the FPGA’s performed as well as the TI or Sony.
For performance results of the Sony / TI / Zetex see my earlier postings in this thread.
The latest Renesas M65818AFP (Ex Mitsubishi - does anybody know if this is the Sony CXD9730?) now has a 1.4MHz (32fs) PWM output mode; I guess this is really only for the “Headphone” mode where Sony suggests to integrate the outputs directly. I speculate that Sony added this mode to reduce the high background noise everybody seems to complain about – not a good thing when you’re listening though headphones. If there is a background hiss problem with Sony products, then the fault lays with the surround circuits, and not their modulator design - as I measured a DR of over 116dB. There’s a new control register to allow summing of the output phases to increase drive current for the headphone circuit.
There’s also three extra modulation formats.
Reading between the lines of the bad “Japanese English” I believe there’s AD, BD and 2 other modes (forms 3 & 4) I don’t fully understand, maybe an inter-channel Phase shifted variant to reduce the net RF emissions of the output stages? The older Sony CXD9634Q / M65817AFP only had 16fs PWM rate (768KHz) and AD modulation.
An interesting limitation with Sony’s BD modulation (Mode 2) is that it will only operate if the Noise Shaper is set to 5Bits, and @ 768KHz. Having to reduce the Noise Shaper to 5Bits seems a major limitation.
Hi TT,
Best regards,
Jaka Racman
really looking forward for that. In my early days I actually built and tested the circuit and the results were quite astonishing. One of the most interesting effects was the ability to control volume of the FM radio playing in the neighbouring room, and the other was that it actually had negative switching time on my Tek scope (EMI caused ray to backtrace durig the switching transient).
Best regards,
Jaka Racman
Hi JohnW,
If I understand your expanation , this means that the M65818 can produce a poorer owerall sound quality however they uses an 1.4MHz PWM output... Is this right?
In the case, you are not sure about it, I may can try a power stage together with the TI and the Renesas chip and will see wich one sounds better...
My first models in MC7 shows that from the TI's output to the power output into the out filter I can still be inside of an owerall (in or out) Delay of 10nS with a jitter <100pSec...
For the power suply stabilising and audio output damping factor increasing I have some solutions...
Cheers,
TT
If I understand your expanation , this means that the M65818 can produce a poorer owerall sound quality however they uses an 1.4MHz PWM output... Is this right?
In the case, you are not sure about it, I may can try a power stage together with the TI and the Renesas chip and will see wich one sounds better...
My first models in MC7 shows that from the TI's output to the power output into the out filter I can still be inside of an owerall (in or out) Delay of 10nS with a jitter <100pSec...
For the power suply stabilising and audio output damping factor increasing I have some solutions...
Cheers,
TT
new in this forum
Hello,
coming from the german
hifi-forum.de » Stereo » Elektronik » Digitale Endstufe DIY-Projekt
(and still participating in the future) we began a class-d project also, based on the Sörensen-project. The first prototype worked in principle (and sounded "a bit"), but I have some beginner's trouble especially at the power stage, still after modifying it with Schottkies and FREDs. Just now I'm trying to convert the power stage to an N-channel stage for higher (and cooler) power handling.
Your thread is interesting, because most of you seem to have some real experience.
I'm very interested in a bit knowledge of fast switching moderate currents and voltages (target: up to around +/- 100V, 25A). In that case, many thanks for the patent-link. It is interesting, also if it may be not the solution.
I hope, I can pay back sometimes a bit for your helpful hints.
regards, tiki
Hello,
coming from the german
hifi-forum.de » Stereo » Elektronik » Digitale Endstufe DIY-Projekt
(and still participating in the future) we began a class-d project also, based on the Sörensen-project. The first prototype worked in principle (and sounded "a bit"), but I have some beginner's trouble especially at the power stage, still after modifying it with Schottkies and FREDs. Just now I'm trying to convert the power stage to an N-channel stage for higher (and cooler) power handling.
Your thread is interesting, because most of you seem to have some real experience.
I'm very interested in a bit knowledge of fast switching moderate currents and voltages (target: up to around +/- 100V, 25A). In that case, many thanks for the patent-link. It is interesting, also if it may be not the solution.
I hope, I can pay back sometimes a bit for your helpful hints.
regards, tiki
Hi TT,
I have a better idea. My simulation shows that by using a simple 5MHz triangle generator and comparator with 1e9 gain and <1nV offset you can have a true natural sampled PWM modulator (superior to uniform sampled PWM that TI uses) with less than 1ps of jitter. And that is at 5MHz, (suitable for your power stage), not some miserable 384kHz that TI uses.
Best regards,
Jaka Racman
I have a better idea. My simulation shows that by using a simple 5MHz triangle generator and comparator with 1e9 gain and <1nV offset you can have a true natural sampled PWM modulator (superior to uniform sampled PWM that TI uses) with less than 1ps of jitter. And that is at 5MHz, (suitable for your power stage), not some miserable 384kHz that TI uses.
Best regards,
Jaka Racman
If 50 kHz isn't achievable then it is indeed a problem of the technology per se (or how it is implemented) and not the switching frequency. 50 kHz bandwidth should not be a problem with a switching frequency of 384 kHz.
Since timing-precision is important for a switching amp (particularly for one without feedback) also an amp with a "low" switching-frequency would profit from a very fast output stage.
Regards
Charles
Hi Jaka,
In the simulated world - okay, but in reality?
The best choppers I know exhibit an offset around 1µV or a bit less, but at a speed...
Triangle generators with 5MHz and, let's say, an 2Vpp amplitude have an output with 20V/µs and will need an Full Power(!) Bandwith of well above 10 times the triangle frequency therefore. This is extremely important at the inflection points and for the linearity, especially, if you use a design without NFB (unregulated). I did some simulations in pspice for triangle generators and also built up two or three (IMO fast) ones, but without any linearity measurements.
And - do you know existing comparators with that outstanding gain of 180dB? May be, a self made one, but would this be fast enough? Possibly a composite design.
If you can, try to use exact models in your simulation environment, I know well, this is sometimes impossible without dividing the whole design into modules.
Or, did I fall for your irony?
Best regards,
tiki
In the simulated world - okay, but in reality?
The best choppers I know exhibit an offset around 1µV or a bit less, but at a speed...
Triangle generators with 5MHz and, let's say, an 2Vpp amplitude have an output with 20V/µs and will need an Full Power(!) Bandwith of well above 10 times the triangle frequency therefore. This is extremely important at the inflection points and for the linearity, especially, if you use a design without NFB (unregulated). I did some simulations in pspice for triangle generators and also built up two or three (IMO fast) ones, but without any linearity measurements.
And - do you know existing comparators with that outstanding gain of 180dB? May be, a self made one, but would this be fast enough? Possibly a composite design.
If you can, try to use exact models in your simulation environment, I know well, this is sometimes impossible without dividing the whole design into modules.
Or, did I fall for your irony?
Best regards,
tiki
power stage principle
That's why I like the self-oscillating principle. Works at 400kHz to 1MHz, depending a bit on the modulation factor. The feedback is part of the principle. See Philips/Hypex and others. They rely on this design, added by a more sophisticated multiloop feedback, with great results (written by them, not heard by me). A disadvantage is the varying frequency. This may possibly be avoided by using a current mode principle like at voltage converters. It triggers the output stage with a defined frequency and varies the pulse width, dependent on the output error.
Regards, tiki
That's why I like the self-oscillating principle. Works at 400kHz to 1MHz, depending a bit on the modulation factor. The feedback is part of the principle. See Philips/Hypex and others. They rely on this design, added by a more sophisticated multiloop feedback, with great results (written by them, not heard by me). A disadvantage is the varying frequency. This may possibly be avoided by using a current mode principle like at voltage converters. It triggers the output stage with a defined frequency and varies the pulse width, dependent on the output error.
Regards, tiki
Hi Charles,
my point was that my analog modulator simulates well and is perfect companion for simulated 5MHz PWM modulated 275V 65A (4kW into 2-8ohm) hard switched full bridge with 2ns transition times that also simulates well. Original poster also wanted analog input. There is no need for feedback when one uses such a fast output stage and such a high quality modulator since there is no error.
Tiki,
with reality in mind and regarding your question, at this time I have no better idea than to point you at the following patent from Spectron. Sorry, but I will start with output stage after I finish my modulator board with TI chips. So far I have made some power stages up to 100V 25A with up to 700kHz switching frequency, but I was not entirely satisfied. They were a bit complicated (transformer coupled drivers and floating gate drive power supplies using large number of small 2.5 and 4 mm toroidal transformers). I can send you Protel schematics, but it might be easier to start with IRF2100 series of half bridge drivers.
Best regards,
Jaka Racman
my point was that my analog modulator simulates well and is perfect companion for simulated 5MHz PWM modulated 275V 65A (4kW into 2-8ohm) hard switched full bridge with 2ns transition times that also simulates well. Original poster also wanted analog input. There is no need for feedback when one uses such a fast output stage and such a high quality modulator since there is no error.
Tiki,
with reality in mind and regarding your question, at this time I have no better idea than to point you at the following patent from Spectron. Sorry, but I will start with output stage after I finish my modulator board with TI chips. So far I have made some power stages up to 100V 25A with up to 700kHz switching frequency, but I was not entirely satisfied. They were a bit complicated (transformer coupled drivers and floating gate drive power supplies using large number of small 2.5 and 4 mm toroidal transformers). I can send you Protel schematics, but it might be easier to start with IRF2100 series of half bridge drivers.
Best regards,
Jaka Racman
Sorry guys,
I have made a mistake the jitter is not below 100pSec. It is below 1000pSec....
Why do you think 50kHz bandwith is not reachable with the TI TAS5015?
While very hi speed switching can be made, the losses are greater of course. And if I use a high speed, accurate power stage for just 384 kHz, it will produce mutch less distortion in the audio signal I guess.
It would be a great thing if TI would come out with a new 768kHz modulator type...
cheers,
TT
I have made a mistake the jitter is not below 100pSec. It is below 1000pSec....
Why do you think 50kHz bandwith is not reachable with the TI TAS5015?
While very hi speed switching can be made, the losses are greater of course. And if I use a high speed, accurate power stage for just 384 kHz, it will produce mutch less distortion in the audio signal I guess.
It would be a great thing if TI would come out with a new 768kHz modulator type...
cheers,
TT
Hello Rookie!
I'm a student from Kunszentmárton, Hungary. I saw your topic about TAS5015. I built a digital amplifier at April last year with the CS8416, TAS3001, and TAS5012. The output stage worked at 100V 25A per outputs. The main disadvantage of this circuit was the feedbackless operation, thus at the area of output currents equal with the coil currents, the dead times cause distortion. The vaweforms are beautiful without load, but with output load the output signal is flattened at that current range. The other advantage of the feedback maybe the output phase shift correction. The normal LC integrator works good with resistive load, but the loudspeakers AREN'T resistive! Nowadays I would like to design an analog output stage with feedback, controlled with the D/A-ed signal of the digital stage. I also would like to do a DSP controlled amplifier with feedback. But I think these are just dreams, the things became so complicated. The schematics are in CorelFLOW 2.0 format.
Best regards!
Gyula
I'm a student from Kunszentmárton, Hungary. I saw your topic about TAS5015. I built a digital amplifier at April last year with the CS8416, TAS3001, and TAS5012. The output stage worked at 100V 25A per outputs. The main disadvantage of this circuit was the feedbackless operation, thus at the area of output currents equal with the coil currents, the dead times cause distortion. The vaweforms are beautiful without load, but with output load the output signal is flattened at that current range. The other advantage of the feedback maybe the output phase shift correction. The normal LC integrator works good with resistive load, but the loudspeakers AREN'T resistive! Nowadays I would like to design an analog output stage with feedback, controlled with the D/A-ed signal of the digital stage. I also would like to do a DSP controlled amplifier with feedback. But I think these are just dreams, the things became so complicated. The schematics are in CorelFLOW 2.0 format.
Best regards!
Gyula
Hi Guys,
Pls. Pls. lets get some reality back to this forum…. Jaka Pls. don’t mention that you have a 70Kg Volume control – you will have all the Krell & ML owners and there ilk, foaming from the sides of there mouths (and other places I’d rather not contemplate) – you know the ones – the ones with interconnect cables the diameter of drain pipes, terminated with more gold and precious metal then your average Rappers apparel… 5MHz @ 2KW? Why?? what for?? Are you trying to make yourselves sterile?
Jaka, you must be a very brave man – I hide under the bench anytime I power-up my 100W output stages – forget one with a 70Kg 3 PHASE Gain control!!!
I guess it goes something like this - $50 for the replacement output devices who unselfishly sacrificed themselves to save the 10 Cent fuses, & $15 for a clean pair of underwear for the freshly hairless Engineer!
1. No - I’m not suggesting that the SONY will sound poor at 1.4MHz, but if used with your average output stage design – it just might. Running the TI output stages at 768KHz is pushing them – don’t try to switch them any higher. Due to the greater errors introduced by the increased switching edges at higher PWM rates, any output stage will exhibit poorer performance then if where operated at slower speeds. If you observe the edges, you will see “Jitter” or “Modulation” as the output current increases – due to there semi – undefined state.
Even with a good driver stage, due to package inductance and more critically the Gate Resistance of the die, there is a limit as to how much instantaneous Gate current a MOSFET can accept to control the depletion layer. MOSFET manufactures strive to optimise the RdsOn value for a given Die area, and wrongly assume that the Gate distribution metalisation does not carry any significant current. Of cause, this is not the case during any attempt to charge and subsequently discharge the Gate capacitance. IR devices are very poor fast switchers, where as Vishay Siliconix are very good – if not the best.
2. As Jaka has pointed out, the biggest issue with Bi-polar transistors is there Storage charge – There is no way to overcome this, although an Emitter follower configuration does not exhibit Storage charge – but then you don’t have any voltage gain. With today’s MOSFET technology, there’s no good reason to try to use Bi-polar's as output devices – you will never achieve the switching linearity of a MOSFET.
3. With a analogue PWM modulator (continues time) with a Triangle carrier, the modulator is inherently linear, with no forward distortions. With a 300KHz PWM rate, it should be no problem to achieve a 50KHz BW. I have Class D designs where the end distortion is limited by the opamps driving the modulator.
The same holds true for a discrete time digital modulator, the limiting factor is the noise shaping power, and the PWM linearizer. With a good 786KHz modulator design, we will one day see a true 50KHz bandwidth. Switching faster then 768KHz removes the whole reason of Class D – namely high efficiency (even 768KHz is really too fast).
I don’t agree that higher switching rates remove the need for feedback – quite the opposite, higher switching rates = greater error due to switching. The dominant distortion factors are PSU & RdsOn non-linearity’s – are removed neither by increasing - nor for that matter by reducing the PWM fs.
Pls. back to sensible ideas & post… and let’s save and preserve what little hair we may have left - not to mention complete DNA strands!
Pls. Pls. lets get some reality back to this forum…. Jaka Pls. don’t mention that you have a 70Kg Volume control – you will have all the Krell & ML owners and there ilk, foaming from the sides of there mouths (and other places I’d rather not contemplate) – you know the ones – the ones with interconnect cables the diameter of drain pipes, terminated with more gold and precious metal then your average Rappers apparel… 5MHz @ 2KW? Why?? what for?? Are you trying to make yourselves sterile?
Jaka, you must be a very brave man – I hide under the bench anytime I power-up my 100W output stages – forget one with a 70Kg 3 PHASE Gain control!!!
I guess it goes something like this - $50 for the replacement output devices who unselfishly sacrificed themselves to save the 10 Cent fuses, & $15 for a clean pair of underwear for the freshly hairless Engineer!
1. No - I’m not suggesting that the SONY will sound poor at 1.4MHz, but if used with your average output stage design – it just might. Running the TI output stages at 768KHz is pushing them – don’t try to switch them any higher. Due to the greater errors introduced by the increased switching edges at higher PWM rates, any output stage will exhibit poorer performance then if where operated at slower speeds. If you observe the edges, you will see “Jitter” or “Modulation” as the output current increases – due to there semi – undefined state.
Even with a good driver stage, due to package inductance and more critically the Gate Resistance of the die, there is a limit as to how much instantaneous Gate current a MOSFET can accept to control the depletion layer. MOSFET manufactures strive to optimise the RdsOn value for a given Die area, and wrongly assume that the Gate distribution metalisation does not carry any significant current. Of cause, this is not the case during any attempt to charge and subsequently discharge the Gate capacitance. IR devices are very poor fast switchers, where as Vishay Siliconix are very good – if not the best.
2. As Jaka has pointed out, the biggest issue with Bi-polar transistors is there Storage charge – There is no way to overcome this, although an Emitter follower configuration does not exhibit Storage charge – but then you don’t have any voltage gain. With today’s MOSFET technology, there’s no good reason to try to use Bi-polar's as output devices – you will never achieve the switching linearity of a MOSFET.
3. With a analogue PWM modulator (continues time) with a Triangle carrier, the modulator is inherently linear, with no forward distortions. With a 300KHz PWM rate, it should be no problem to achieve a 50KHz BW. I have Class D designs where the end distortion is limited by the opamps driving the modulator.
The same holds true for a discrete time digital modulator, the limiting factor is the noise shaping power, and the PWM linearizer. With a good 786KHz modulator design, we will one day see a true 50KHz bandwidth. Switching faster then 768KHz removes the whole reason of Class D – namely high efficiency (even 768KHz is really too fast).
I don’t agree that higher switching rates remove the need for feedback – quite the opposite, higher switching rates = greater error due to switching. The dominant distortion factors are PSU & RdsOn non-linearity’s – are removed neither by increasing - nor for that matter by reducing the PWM fs.
Pls. back to sensible ideas & post… and let’s save and preserve what little hair we may have left - not to mention complete DNA strands!
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