reconstruction filters
Wow - once again you're a great source of information. I hadn't seen the tech paper before - very very interesting. From some of the posts in the '100mhz oscillator' thread, I noticed that the measurements of the 'full chain' amp showed much higher IMD than JohnW's modulator-only numbers. I had figured that this was due mostly to the output bridge, but this shows that the reconstruction filter is probably the dominant source. Removing the filter is certainly an interesting idea to consider if the drivers can handle it.
Maybe it's time to investigate using shielded romex for speaker cables.
Brian Brown said:
Wow - once again you're a great source of information. I hadn't seen the tech paper before - very very interesting. From some of the posts in the '100mhz oscillator' thread, I noticed that the measurements of the 'full chain' amp showed much higher IMD than JohnW's modulator-only numbers. I had figured that this was due mostly to the output bridge, but this shows that the reconstruction filter is probably the dominant source. Removing the filter is certainly an interesting idea to consider if the drivers can handle it.
Maybe it's time to investigate using shielded romex for speaker cables.
Hi,
I hope this is not the case, but it is more function of interchannel delays set in evaluation board. Quote from datasheet:
Those proposed delay times are not symmetrical, so there is a chance that they are selected to get the best performance in the first two channels.
5182 actually checks mosfet's on voltage which is proportional to Rdson and load current. By using larger mosfets you would profit only if you have low speaker impendance by increasing output current limit. If you would like to use higher supply voltage then you might consider Intersil HIP2101 driver. Of course you would need to provide your own protection circuit.
Best regards,
Jaka Racman
I hope this is not the case, but it is more function of interchannel delays set in evaluation board. Quote from datasheet:
Those proposed delay times are not symmetrical, so there is a chance that they are selected to get the best performance in the first two channels.
5182 actually checks mosfet's on voltage which is proportional to Rdson and load current. By using larger mosfets you would profit only if you have low speaker impendance by increasing output current limit. If you would like to use higher supply voltage then you might consider Intersil HIP2101 driver. Of course you would need to provide your own protection circuit.
Best regards,
Jaka Racman
Brian,
Sorry for the delay in answering – I’ve just return from a business trip.
I’m evaluating the performance of the modulators only, so I’m re-latching their outputs, buffering and then LPF.
With an open-loop output stage, in order of dominants - the distortion factors are: -
PSU
Mosfet RdsOn
Driver circuit
With good inductors, such as Amidon material Type 2 (permeability 10), the inductors performance only becomes a limiting factor (at least from a THD stand point) once the all other Output Stage distortions have been reduced to below 0.002%.
I have not spent much time on improving the inductor performance, as it should be a relatively simple task to improve upon current Amidon performance.
An interesting observation - with an OPS with 0.0002% THD @ 115W 8R pre inductors (so the THD result is measured with a passive LPF directly on FET’s, but with load connected on the inductor side). The distortion introduced by the Amidon inductors is about 0.0015% at ALL power levels until the output is reduced to about 1W, where there is an abrupt STEP drop, and the output from the inductors tracks the THD results at the MOSFET side.
I don’t have an explanation to this “Step Drop”, the clue might be in the distortion components which are largely Low odd order - 3rd, 5th, etc. ST AN1013 talks about “Dead Zone Step”, but the THD on the MOSFET’s side is below 0.0002% at all times – so I’m currently at a loss to explain this phenomenon.
The ST app note does talk about Low odd order harmonic components due to “Non linearity of the permeability with increase in magnetic field”. So I wander what effect “Gapping” the Amidon toroidal cores might have – would it reduce these odd order components?
As has already been pointed out, I was referring to the TI’s stop band above fs/2, from my experience; the greatest sonic advantage gained from “up-sampling” is the improvement in stop-band.
Benchmark Media systems has a very interesting paper on the Web, titled “Jitter and it’s effects”, where jitter is shown to degrade digital Anti-Alias filters Stopband performance – I believe that this effect must also degrade ASRC performance – implying that great care must be taken with the ASRC Secondary master clock (i.e. the output rate master clock).
Also by “Up-sampling” any modulation of the Stopband rejection due to jitter now happens well above the “audio band” – another advantage to “Upsampling” ASRC? I know from design experience that no particular care is take with the phase noise performance of clock distribution paths in digital filters – at least not to the same degree as with the “understood” critical DAC sections.
Sorry for the delay in answering – I’ve just return from a business trip.
I’m evaluating the performance of the modulators only, so I’m re-latching their outputs, buffering and then LPF.
With an open-loop output stage, in order of dominants - the distortion factors are: -
PSU
Mosfet RdsOn
Driver circuit
With good inductors, such as Amidon material Type 2 (permeability 10), the inductors performance only becomes a limiting factor (at least from a THD stand point) once the all other Output Stage distortions have been reduced to below 0.002%.
I have not spent much time on improving the inductor performance, as it should be a relatively simple task to improve upon current Amidon performance.
An interesting observation - with an OPS with 0.0002% THD @ 115W 8R pre inductors (so the THD result is measured with a passive LPF directly on FET’s, but with load connected on the inductor side). The distortion introduced by the Amidon inductors is about 0.0015% at ALL power levels until the output is reduced to about 1W, where there is an abrupt STEP drop, and the output from the inductors tracks the THD results at the MOSFET side.
I don’t have an explanation to this “Step Drop”, the clue might be in the distortion components which are largely Low odd order - 3rd, 5th, etc. ST AN1013 talks about “Dead Zone Step”, but the THD on the MOSFET’s side is below 0.0002% at all times – so I’m currently at a loss to explain this phenomenon.
The ST app note does talk about Low odd order harmonic components due to “Non linearity of the permeability with increase in magnetic field”. So I wander what effect “Gapping” the Amidon toroidal cores might have – would it reduce these odd order components?
As has already been pointed out, I was referring to the TI’s stop band above fs/2, from my experience; the greatest sonic advantage gained from “up-sampling” is the improvement in stop-band.
Benchmark Media systems has a very interesting paper on the Web, titled “Jitter and it’s effects”, where jitter is shown to degrade digital Anti-Alias filters Stopband performance – I believe that this effect must also degrade ASRC performance – implying that great care must be taken with the ASRC Secondary master clock (i.e. the output rate master clock).
Also by “Up-sampling” any modulation of the Stopband rejection due to jitter now happens well above the “audio band” – another advantage to “Upsampling” ASRC? I know from design experience that no particular care is take with the phase noise performance of clock distribution paths in digital filters – at least not to the same degree as with the “understood” critical DAC sections.
TAS5015+5111+SRC4192
Hi !
TAS5015 in a master mode, +2x TAS5111+SRC4192 - works perfectly third day...
I found Crystek C3392 125 MHz (!!) lo jitter (hmmm 3ps) oscillator (powered from low noise (15mikroV) reg.) as a HFClock...and TAS at 122kHz fps (488kHz power stage) works...
Really works... I'm afraid so high clock, but... it works :-O
Powered 2xOPA549 (as a previous model RyTM) ... beautyful sound
Best Regards
JaroMi
(full power(33V PVDD), all zeros - any audible noise... previously a little, now-any I'm so glad
I'm sorry again my bad-basic english......
Hi !
TAS5015 in a master mode, +2x TAS5111+SRC4192 - works perfectly third day...
I found Crystek C3392 125 MHz (!!) lo jitter (hmmm 3ps) oscillator (powered from low noise (15mikroV) reg.) as a HFClock...and TAS at 122kHz fps (488kHz power stage) works...
Really works... I'm afraid so high clock, but... it works :-O Powered 2xOPA549 (as a previous model RyTM) ... beautyful sound
Best Regards
JaroMi
(full power(33V PVDD), all zeros - any audible noise... previously a little, now-any
I'm so glad I'm sorry again my bad-basic english......
Wich sounds better?
Hi,
Just seen this thread.
I was started experimenting with PWM amps 8-9 years ago.
Now I am interrested for a full digital amp like those with the TIs equibit chip.
As I understand the Panasonic SA-XR series uses this chipset and sounds good.
My question is, sounds those as good as the TACT Millenium?
My other question:
I have seen the Mitsubishi's M65817 and M65818 DSD/PCM to PWM chips. Does they sound better than the TI chips?
I don't know wich technique they uses should sound better than the Equibit Technique?
I want to build a good sounding Pro audio amp with AES/EBU PCM and With DSD and with an Analogue input.
They should have a SMPS and should produce an output power of 2x2-4 kW into 2-8 Ohm loads with small output impedance and shold have a bandwith of at least 50kHz.
With one word this should be a power DAC or when used with the analogue input a power ADC-DAC.
Thanks,
Tako Tamas
ttako@hit.hu
Hi,
Just seen this thread.
I was started experimenting with PWM amps 8-9 years ago.
Now I am interrested for a full digital amp like those with the TIs equibit chip.
As I understand the Panasonic SA-XR series uses this chipset and sounds good.
My question is, sounds those as good as the TACT Millenium?
My other question:
I have seen the Mitsubishi's M65817 and M65818 DSD/PCM to PWM chips. Does they sound better than the TI chips?
I don't know wich technique they uses should sound better than the Equibit Technique?
I want to build a good sounding Pro audio amp with AES/EBU PCM and With DSD and with an Analogue input.
They should have a SMPS and should produce an output power of 2x2-4 kW into 2-8 Ohm loads with small output impedance and shold have a bandwith of at least 50kHz.
With one word this should be a power DAC or when used with the analogue input a power ADC-DAC.
Thanks,
Tako Tamas
ttako@hit.hu
Re: Wich sounds better?
Hi
How the Panasonic compares with the Tact Millenium i don't know ...but i know, how it compares with the Sony STR-DB 2000....because i have both. First of all, i must say ,that with Sony, i have a great desilusion...the sound is thin ,silvery and tiring...and i hear a hiss bout -10 db of the volume...
A tecnhical point, the panny use a 12 dB per octave post filter the sony a 24 dB one...it seems that Sony are puting the hiss issue "under the carpet" ,
We can never hit always the target...and for me the sony is a "sad tale"
Here you can see the pic of the original STR 2000...
http://www.docs.sony.com/release/STRDA3000ES_TWP.pdf
and compare with mine in this thread
http://www.diyaudio.com/forums/showthread.php?s=&threadid=7754&perpage=15&pagenumber=9
If you compare the pics,you will see that in the original ,the output filter is a LC (12dB octave) filter and in mine you can see LCLC (24dB octave )filter
PS: After 2 years(so the honey moon is gone) and many tweks (thanks Brian) the Panasonic is allways amazing me...the sound quality is incredible!!
ttako said:
Hi
How the Panasonic compares with the Tact Millenium i don't know ...but i know, how it compares with the Sony STR-DB 2000....because i have both. First of all, i must say ,that with Sony, i have a great desilusion...the sound is thin ,silvery and tiring...and i hear a hiss bout -10 db of the volume...
A tecnhical point, the panny use a 12 dB per octave post filter the sony a 24 dB one...it seems that Sony are puting the hiss issue "under the carpet" ,
We can never hit always the target...and for me the sony is a "sad tale"
Here you can see the pic of the original STR 2000...
http://www.docs.sony.com/release/STRDA3000ES_TWP.pdf
and compare with mine in this thread
http://www.diyaudio.com/forums/showthread.php?s=&threadid=7754&perpage=15&pagenumber=9
If you compare the pics,you will see that in the original ,the output filter is a LC (12dB octave) filter and in mine you can see LCLC (24dB octave )filter
PS: After 2 years(so the honey moon is gone) and many tweks (thanks Brian
) the Panasonic is allways amazing me...the sound quality is incredible!!power stage High switching frequ., DSD power DAC
Hi,
I know shematics techniques wich allows easy building hi power switch stages for frequencies up to 4-5 MHz...
Therefore I had the idea to use a direct DSD signal driven full digital "DSD power DAC"
I just would to know how to convert pcm signals into DSD and how to use the DSD for PWM modulating? I know that DSD is 1BIT 2.82MHz digital signal wich I would like to convert into PWM (1 BIT 2.82MHz).
But I think DSD DACs uses some special noise shaping techniques and works not as simple as a single integrator in the high freq delta sigma 1 BIT DACs...
Can anybody help me?
Thanks,
Tako Tamas
Hi,
I know shematics techniques wich allows easy building hi power switch stages for frequencies up to 4-5 MHz...
Therefore I had the idea to use a direct DSD signal driven full digital "DSD power DAC"
I just would to know how to convert pcm signals into DSD and how to use the DSD for PWM modulating? I know that DSD is 1BIT 2.82MHz digital signal wich I would like to convert into PWM (1 BIT 2.82MHz).
But I think DSD DACs uses some special noise shaping techniques and works not as simple as a single integrator in the high freq delta sigma 1 BIT DACs...
Can anybody help me?
Thanks,
Tako Tamas
Why do you want to do so ?
The DSD signal is already a pulse-density modulated signal. If you build a precise switching stage for it, you will end up with a delat-sigma switching amp (I don't want to claim that it would be easy though). But I don't know whether you would have access to it because manufacturers are very reluctant to let you access the bare DSD signal somewhere in the chain.
Regards
Charles
Hi,
That is truly amazing. Could you elaborate a little about that? So far I have thought only Directed Energy (now IXYS) mosfets and drivers a capable of something like that.
As you can see from this post TAS5015 has BD modulated outputs and is therefore suitable for BCA power stage.
Regarding DSD, here is excerpt from Bruno Putzeys opinion posted in RAHE:
Bruno Putzeys is author of multiphase direct DSD input amplifier which he considers to be of lower quality than his UCD amplifier.
Best regards
Jaka Racman
That is truly amazing. Could you elaborate a little about that? So far I have thought only Directed Energy (now IXYS) mosfets and drivers a capable of something like that.
As you can see from this post TAS5015 has BD modulated outputs and is therefore suitable for BCA power stage.
Regarding DSD, here is excerpt from Bruno Putzeys opinion posted in RAHE:
Bruno Putzeys is author of multiphase direct DSD input amplifier which he considers to be of lower quality than his UCD amplifier.
Best regards
Jaka Racman
JaroMi, I’ve had the TI output stages running at 768KHz so they should be OK, cannot comment on the Modulator / SRC – be very careful with the M:S ratio of the clock – all to easy to get very narrow pulse widths.
Ttako, at such high power levels I would go for the TI modulator as it has a lower PWM switching rate. I would not recommend an Open loop Digital amplifier at such high power levels – trying to reduce distortion due to PSU / RdsOn / PCB losses will be a nightmare – but then do you really need High Quality at such power levels?
My first “Digital Amplifier” was based upon the SAA7350 PDM outputs at about 6MHz! This unit was a nightmare, as a true one bit system (PWM is not 1 Bit) it was incredibly sensitive to phase noise – also due the inherent nature of PDM modulation you can only use 50% of the voltage available from PSU rails. With DSD DataStream AMP, how would you implement the Gain control? The PSU can only be reduced to about 5V to 10V depending on the Gate driver circuit (you would also have to maintain the pulse linearity at these low levels) – what about positive digital Gain? - I’d forget PDM/DSD for a digital amp!
For a good application of RAW PDM look at the CS4303 Eval board application notes – in fact I use the old CS4303 as a DSD generator – although its “only” a 5th order noise shaper. All 1Bit ADC / DAC’s that I’m aware of use multi order noise shaping (integrators), the correction factor of a simple first Order is too low for acceptable performance.
The DSD DataStream is available internal to a product – look at the pin connections to the M65817 / M65818.
Thanks for the STR DA3000ES link - what a load of marketing BULL! – Needed a laugh!
E.g.: -
Synchronous Time Accuracy controller “S-Tact” = D type Latch!
Clean Data Cycle = SRC
Complementary Pulse Length Modulation (Sony claims IT developed
) “C-PLM” = Full H-Bridge!
Pulse Height Volume Control = Variable PSU
ES Engineers choose EXOTIC! Toroidal Cores – Yes, so does my bedroom light dimmer!
Deluxe (No less) Metal Oxide Semiconductor FETs = Err… MOSFET’s
And the Crap goes on – but I like the principle behind Output module Pg. 26, see next page for the “Deluxe” MOSFET die mounting, but only 2 “Source” bonding wires (mind you it’s a very small die) – and a Resister on the Gate combined with the very thin Gate distribution ring around the perimeter & Centre of the Die – guaranteeing slow Turn off = high switching losses.
Ttako, at such high power levels I would go for the TI modulator as it has a lower PWM switching rate. I would not recommend an Open loop Digital amplifier at such high power levels – trying to reduce distortion due to PSU / RdsOn / PCB losses will be a nightmare – but then do you really need High Quality at such power levels?
My first “Digital Amplifier” was based upon the SAA7350 PDM outputs at about 6MHz! This unit was a nightmare, as a true one bit system (PWM is not 1 Bit) it was incredibly sensitive to phase noise – also due the inherent nature of PDM modulation you can only use 50% of the voltage available from PSU rails. With DSD DataStream AMP, how would you implement the Gain control? The PSU can only be reduced to about 5V to 10V depending on the Gate driver circuit (you would also have to maintain the pulse linearity at these low levels) – what about positive digital Gain? - I’d forget PDM/DSD for a digital amp!
For a good application of RAW PDM look at the CS4303 Eval board application notes – in fact I use the old CS4303 as a DSD generator – although its “only” a 5th order noise shaper. All 1Bit ADC / DAC’s that I’m aware of use multi order noise shaping (integrators), the correction factor of a simple first Order is too low for acceptable performance.
The DSD DataStream is available internal to a product – look at the pin connections to the M65817 / M65818.
Thanks for the STR DA3000ES link - what a load of marketing BULL! – Needed a laugh!
E.g.: -Synchronous Time Accuracy controller “S-Tact” = D type Latch!
Clean Data Cycle = SRC
Complementary Pulse Length Modulation (Sony claims IT developed
) “C-PLM” = Full H-Bridge!Pulse Height Volume Control = Variable PSU
ES Engineers choose EXOTIC! Toroidal Cores – Yes, so does my bedroom light dimmer!
Deluxe (No less) Metal Oxide Semiconductor FETs = Err… MOSFET’s
And the Crap goes on – but I like the principle behind Output module Pg. 26, see next page for the “Deluxe” MOSFET die mounting, but only 2 “Source” bonding wires (mind you it’s a very small die) – and a Resister on the Gate combined with the very thin Gate distribution ring around the perimeter & Centre of the Die – guaranteeing slow Turn off = high switching losses.
Hi JonhWJohnW said:
Thanks for the STR DA3000ES link - what a load of marketing BULL! – Needed a laugh!
Synchronous Time Accuracy controller “S-Tact” = D type Latch!
Clean Data Cycle = SRC
Complementary Pulse Length Modulation (Sony claims IT developed
Pulse Height Volume Control = Variable PSU
ES Engineers choose EXOTIC! Toroidal Cores – Yes, so does my bedroom light dimmer!
Deluxe (No less) Metal Oxide Semiconductor FETs = Err… MOSFET’s
And the Crap goes on – but I like the principle behind Output module Pg. 26, see next page for the “Deluxe” MOSFET die mounting, but only 2 “Source” bonding wires (mind you it’s a very small die) – and a Resister on the Gate combined with the very thin Gate distribution ring around the perimeter & Centre of the Die – guaranteeing slow Turn off = high switching losses.
Yes the Sony has been for me a desilusion...i think that their marketing team is doing a better job than the projecting team!!!
Hi JohnW,
Thanks for your post.
Could you tell me how can I run my TAS5015 outputs @768kHz?
Thanks,TT
For some high freq. switching you just have to look at the passlabs' website for inventions.
They invented a special floating DC cascade power stage for audio. this is very suitable for hi frequ.
Thanks,
TT
Thanks for your post.
Could you tell me how can I run my TAS5015 outputs @768kHz?
Thanks,TT
For some high freq. switching you just have to look at the passlabs' website for inventions.
They invented a special floating DC cascade power stage for audio. this is very suitable for hi frequ.
Thanks,
TT
The Pass's invention Is US patent 5,343,166 for the high frequ switching. This is an easy setup wich U can use with MOSFET input and Bipolar cascade stage... Becouse of the DC on the driven Mosfet's Gate-Drain this Miller cap. doesn't matter any more!!! And the DC floating on the output can set to 12 or 5 V.so the driven Mosfets should not withstand high Uds....
cheers,
TT.
cheers,
TT.
Hi TT,
Field Programmable Gate Array – allow you to create very large digital designs, and program them into your own chip.
While simulators verify the electrical operation of a design – the biggest cause (80%) of IC re-spins (corrections to a design) is device functionally e.g. makes noises while changing modes, gain etc. If you don’t know what to look for, these types of “issues” are very hard to simulate.
An FPGA allow verification of design & functionality of an IC design before being committed to hard silicon – unfortunately, FPGA’s don’t allow accurate “prototypes” of PLL’s – one of the hardest things to get right first time.
Field Programmable Gate Array – allow you to create very large digital designs, and program them into your own chip.
While simulators verify the electrical operation of a design – the biggest cause (80%) of IC re-spins (corrections to a design) is device functionally e.g. makes noises while changing modes, gain etc. If you don’t know what to look for, these types of “issues” are very hard to simulate.
An FPGA allow verification of design & functionality of an IC design before being committed to hard silicon – unfortunately, FPGA’s don’t allow accurate “prototypes” of PLL’s – one of the hardest things to get right first time.
Digital chips...
Hi Digital friends!!
These are the chips that i think Sony use...of course with other names.
http://www.renesas.com/avs/resource/japan/eng/pdf/assp/rej03f0019_m65818afp.pdf
Hi Digital friends!!
These are the chips that i think Sony use...of course with other names.
http://www.renesas.com/avs/resource/japan/eng/pdf/assp/rej03f0019_m65818afp.pdf
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