That is a SAA7220 bypass board. FWIW, the Ian board also uses logic gates.
Hi rfbrw,
Is there much difference in the way programmable logic works like in Ians gear, and actual logic gates in separate packages - like what Johns circuit uses? I'd imagine better isolation from from the inputs?
Simultaneous mode would need mode changing on the TDA1541A. There is nothing like this mentioned in the item description. I suppose this is just a digital filter bypass board, i.e. NOS mod, with optional mute.
imho the most straighforward way of operating the TDA1541A in simultanious mode is probably the JLsounds I2SoverUSB v3.
That is USB=>XMOS=>isolation=>reclocking/format CPLD=>isolation(?)=>DAC. I bought one as JLsounds also provides ASIO drivers. Still waiting for the updated documentation... I'll using it with 2xTDA in balanced and with the low frequency ECDesign DEM. Will report back once its running.
That is USB=>XMOS=>isolation=>reclocking/format CPLD=>isolation(?)=>DAC. I bought one as JLsounds also provides ASIO drivers. Still waiting for the updated documentation... I'll using it with 2xTDA in balanced and with the low frequency ECDesign DEM. Will report back once its running.
Hi koldby,
TDA1543 has fixed I2S interface so it can't receive two data streams simultaneously.
We could modify the signed magnitude decoder so it outputs two I2S streams instead of 4 separate data streams, one for each TDA1543. This has the disadvantage that we always have trigger uncertainty due to digital interface activity and related crosstalk and ground-bounce during output latching.
But we could also apply quasi simultaneous mode, this would require 4 x TDA1543 and only a slight modification to the existing decoder
Quasi simultaneous mode:
- clock in R channel data while WS = 1 (we can only use the R channel / segment).
- Shut down interface (BCK and data) and wait for WS to go low.
- Wait another 16 bits and then latch the outputs with one extra pulse (LE) on BCK when ground-bounce and crosstalk have reached zero.
TDA1543A latches its outputs on the first rising edge of BCK after WS has gone low. If this single BCK pulse is delayed we can change the exact moment of output latching. This is only possible when we do not use the L channel.
It makes a lot of sense to operate the TDA1543 in segmented mode as this would eliminate the audibility of MSB related bit errors (big problem with the TDA1543) in this zero crossing region.
TDA1543 chips are not graded so you will have chips with high accuracy, chips that perform good, chips that perform too badly to be of any practical use and few that will be defective.
Roughly 5% of a larger batch (100+) of TDA1543 chips will perform pretty good and will have good channel matching.
Similar to the TDA1541, the TDA1543 transistors will need to have the same temperature for optimal accuracy (emitter scaling). This usually requires a warm-up period of at least half an hour or longer. This means that the chip will produce higher distortion (and related poorer sound quality) during this warm-up period.
The mentioned double zero code is corrected by ensuring that bit 15 of each segment (each represents 0.5 LSB in a segmented DAC) follows the MSB. This effectively adds one LSB, only when MSB = 1.
TDA1543 has fixed I2S interface so it can't receive two data streams simultaneously.
We could modify the signed magnitude decoder so it outputs two I2S streams instead of 4 separate data streams, one for each TDA1543. This has the disadvantage that we always have trigger uncertainty due to digital interface activity and related crosstalk and ground-bounce during output latching.
But we could also apply quasi simultaneous mode, this would require 4 x TDA1543 and only a slight modification to the existing decoder
Quasi simultaneous mode:
- clock in R channel data while WS = 1 (we can only use the R channel / segment).
- Shut down interface (BCK and data) and wait for WS to go low.
- Wait another 16 bits and then latch the outputs with one extra pulse (LE) on BCK when ground-bounce and crosstalk have reached zero.
TDA1543A latches its outputs on the first rising edge of BCK after WS has gone low. If this single BCK pulse is delayed we can change the exact moment of output latching. This is only possible when we do not use the L channel.
It makes a lot of sense to operate the TDA1543 in segmented mode as this would eliminate the audibility of MSB related bit errors (big problem with the TDA1543) in this zero crossing region.
TDA1543 chips are not graded so you will have chips with high accuracy, chips that perform good, chips that perform too badly to be of any practical use and few that will be defective.
Roughly 5% of a larger batch (100+) of TDA1543 chips will perform pretty good and will have good channel matching.
Similar to the TDA1541, the TDA1543 transistors will need to have the same temperature for optimal accuracy (emitter scaling). This usually requires a warm-up period of at least half an hour or longer. This means that the chip will produce higher distortion (and related poorer sound quality) during this warm-up period.
The mentioned double zero code is corrected by ensuring that bit 15 of each segment (each represents 0.5 LSB in a segmented DAC) follows the MSB. This effectively adds one LSB, only when MSB = 1.
Everything about the humble little chip interests me.
My dual-mono and "scrambler-interpolator" DACs are still sounding sweet and dynamic but, if there are less noisy circuits out there, I'm all ears.
I've seen offerings about a TDA1543"A" chip. Which are these?
Thanks, Master.
Best wishes,
M.
My dual-mono and "scrambler-interpolator" DACs are still sounding sweet and dynamic but, if there are less noisy circuits out there, I'm all ears.
I've seen offerings about a TDA1543"A" chip. Which are these?
Thanks, Master.
Best wishes,
M.
Maxlorenz, the TDA1543A is also a 16 bit dac, based on the TDA1543, however it works with 24 bit right justified format. Due to market demand probably, back in the time of CD players.
Some other differences:
TDA1543A channels latch simultaneously, unlike TDA1543 which shows a delay of 1 bitclock period between channels, assuming I2S input.
(BTW I don´t use I2S with plain TDA1543, I use my own version of the stopped clock for right channel only).
If you use TDA1543A and passive I/V, it doesn´t show the severe low level distortion which plain TDA1543 shows on the left channel only.
There may be other differences between the two, I personally prefer the plain TDA1543 with stopped clock method.
Thanks
Alex
Some other differences:
TDA1543A channels latch simultaneously, unlike TDA1543 which shows a delay of 1 bitclock period between channels, assuming I2S input.
(BTW I don´t use I2S with plain TDA1543, I use my own version of the stopped clock for right channel only).
If you use TDA1543A and passive I/V, it doesn´t show the severe low level distortion which plain TDA1543 shows on the left channel only.
There may be other differences between the two, I personally prefer the plain TDA1543 with stopped clock method.
Thanks
Alex
I have always noticed this
I thought of it too, pretty easy and inexpensive solution, but the result is no longer a 17 bit dac, which was one of the advantages of the segmented dac. I might go for the complex solution and implement the adder. (But not with tda1543... I´m interested in doing this with tda1541.)
Thanks,
Alex
Is it sufficient to leave it powered up but idle? Or does it need to be processing data in order to heat the transistors. Perhaps a dumb question, but I leave the TDA1541A powered 7/24 but still the system sounds better after playing for 30 mins. I assumed it was the amp that was mellowing out but now I wonder if it is the DAC.
I also think that Ian's board allows 192kHz operation if that interests anyone. By the look of the I2S-to-TDA board in this thread, the BCLK signal is unchanged from its original bitrate (even though it only appears in bursts) and would only allow operation up to 96kHz due to the 6.144MHz limit of the TDA1541 clock input.
I've been lazy to perform the "R channel only output" for my dual-mono TAD1543 DAC.
With that connection, will the chips still use the same current or half the current???
Thanks,
M.
..............
I've seen offerings about a TDA1543"A" chip. Which are these?
Thanks, Master.
Best wishes,
M.
The A variant is for a format favoured by Sony in days gone by. Right justified, 24 bits per sub-frame and BCLK is multiples of 48Fs only.
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Max, same current. Each TDA1543 draws 50mA no matter what.I've been lazy to perform the "R channel only output" for my dual-mono TAD1543 DAC.
With that connection, will the chips still use the same current or half the current???
Thanks,
M.
-Alex
Merrill, those measurements are not looking good. Amplitude error for low level signals is not that bad on the right channel. See here for another TDA1543 with passive I/V:
47 Laboratory 4715 D/A processor & 4716 CD transport Measurements | Stereophile.com
Notice that the -90dB sinewave is shown for the left channel only (worse). I expect the -90dB sine with a selected chip to look much better on the right channel. This is diy, if it gives a good result we can use only the right channel of the chips
(Tda1543 is nice to listen to, but is not the most detailed dac)
-Alex
47 Laboratory 4715 D/A processor & 4716 CD transport Measurements | Stereophile.com
Notice that the -90dB sinewave is shown for the left channel only (worse). I expect the -90dB sine with a selected chip to look much better on the right channel. This is diy, if it gives a good result we can use only the right channel of the chips
(Tda1543 is nice to listen to, but is not the most detailed dac)
-Alex
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