Building the ultimate NOS DAC using TDA1541A

[roger57]

Maarten,

Have you thought about trying a buffer between the WS and the DEM circuitry? That would unload WS as the buffer would supply the drive current. An inverter/buffer like the NC7S04 has minimal propagation delay of 3ns

Gary

How important is jitter in the DEM signal anyway?
I am now injecting a derivative of my (not reclocked) WS signal into the DEM oscillator, and confirmed it is locked (visible 4-step signal on the decoupling pins). I am using an smd schottky diode and some resistors between pin1 and pin16.

1. Of course, with DEM be synchronized to WS, some of the problems with crosstalk outlined by John are mitigated, regardless of whether the WS signal is jittery or not (point being is that they are synchronous).

2. A not-reclocked WS signal should be ok as input signal as BCK (which is reclocked in my case) provides the timing for the latching.

However, now that WS becomes the driver for the DEM oscillator as well, what is the impact of any jitter on the WS (= DEM Oscillator) signal?

btw, sounds pretty darn good, much softer/smoother in the mids and highs, and bass has tightened up as well.

 

[studiostevus]

Maarten,

Have you thought about trying a buffer between the WS and the DEM circuitry? That would unload WS as the buffer would supply the drive current. An inverter/buffer like the NC7S04 has minimal propagation delay of 3ns

Gary

No need.

I was more referring to inherent jitter on the WS signal (not necessarily anything related to the fact it is now driving the DEM Oscillator).

 

[brubeck]

Does everyone commit now that DEM=WS is the best (sound) solution for NOS like Ecdesigns explains? As i understand it doesn't matter that the shift register takes 4 samples to complete. A 1uF capacitor will smoothen these 4 values to a steady average voltage over the samples. So no need to go higher with DEM.

 

[JOSI1]

How important is jitter in the DEM signal anyway?
I am now injecting a derivative of my (not reclocked) WS signal into the DEM oscillator, and confirmed it is locked (visible 4-step signal on the decoupling pins). I am using an smd schottky diode and some resistors between pin1 and pin16.
QUOTE]

Hello studiostevus,

which function has the schottky diode and what resistor value(s) did you use?
I only inserted a resistor but the value seems to be critical, as it only works with a value 100...120k.

 

[lcsaszar]

Does everyone commit now that DEM=WS is the best (sound) solution for NOS like Ecdesigns explains? As i understand it doesn't matter that the shift register takes 4 samples to complete. A 1uF capacitor will smoothen these 4 values to a steady average voltage over the samples. So no need to go higher with DEM.

From the second picture of post #4434 it seems to me that a 4-step pattern is repeated every 4 cycles of the DEM clock, so the pattern's fundamental frequency is 11.025 kHz with a 44.1 kHz harmonic content. This is clearly in the audio band for NOS if the DEM is clocked from WS. It might be filtered by the external DEM capacitor, but doesn't any interference with the audio signal occur inside the chip?

 

[studiostevus]

From the second picture of post #4434 it seems to me that a 4-step pattern is repeated every 4 cycles of the DEM clock, so the pattern's fundamental frequency is 11.025 kHz with a 44.1 kHz harmonic content. This is clearly in the audio band for NOS if the DEM is clocked from WS. It might be filtered by the external DEM capacitor, but doesn't any interference with the audio signal occur inside the chip?

I was thinking the same. Moreover, can intra-sample averaging take place if the effective cycling frequency is only 11mhz?

 

[studiostevus]

How important is jitter in the DEM signal anyway?
I am now injecting a derivative of my (not reclocked) WS signal into the DEM oscillator, and confirmed it is locked (visible 4-step signal on the decoupling pins). I am using an smd schottky diode and some resistors between pin1 and pin16.
QUOTE]

Hello studiostevus,

which function has the schottky diode and what resistor value(s) did you use?
I only inserted a resistor but the value seems to be critical, as it only works with a value 100...120k.

I added the diode to avoid any currents flowing back into the WS signal. Not sure if necessary, just to be sure.

Indeed the resistor value is critical, i used a variable resistor to find the correct value it which the multivibrator locks to the input signal. Then i replaced with a fixed resistor.

Btw, if you need such a high resistor value, i expect you are not using i2s attennuation.... There is still more improvement for you to explore!

 

[ecdesigns]

Hi oshifis,

From the second picture of post #4434 it seems to me that a 4-step pattern is repeated every 4 cycles of the DEM clock, so the pattern's fundamental frequency is 11.025 kHz with a 44.1 kHz harmonic content

From the IEEE journal of solid state circuits vol. SC-14, no.3, June 1979 page 553

"The output currents as function of time are shown in Fig. 3(b). The figure shows that the currents with value I have a ripple with the same frequency as the clock generator f, while the current with value 2I has ripple with a frequency f/2".

Practical measurements on all 14 active divider outputs on a number of different TDA1541A DAC chips all showed a ripple frequency of fDEM.

Each active divider output has different step pattern. There are 3 active dividers used for each channel. The DAC output consists of combinations of these binary weighted filtered DC bit currents.

After filtering, the ripple current is low enough to remain inaudible.

On-chip crosstalk occurs, that's why I use the same frequency (44.1 KHz, synchronized) for both DEM oscillator and WS.

 

[dady]

Good morning John, I am still reading about your topic. You still in ride. Best Best Regards in this sumer from my paradise.
This season i see many Dutch people for my town.

 

[studiostevus]

From the IEEE journal of solid state circuits vol. SC-14, no.3, June 1979 page 553

"The output currents as function of time are shown in Fig. 3(b). The figure shows that the currents with value I have a ripple with the same frequency as the clock generator f, while the current with value 2I has ripple with a frequency f/2".

Practical measurements on all 14 active divider outputs on a number of different TDA1541A DAC chips all showed a ripple frequency of fDEM.

Each active divider output has different step pattern. There are 3 active dividers used for each channel. The DAC output consists of combinations of these binary weighted filtered DC bit currents.

After filtering, the ripple current is low enough to remain inaudible.

On-chip crosstalk occurs, that's why I use the same frequency (44.1 KHz, synchronized) for both DEM oscillator and WS.

For all intends and purposes, has anyone ever measured these artifacts of the DEM clock on the DAC output?

I realize Philips/VanderPlassche refers to it in all his articles, but have we ever actually seen it?

 

[roger57]

John,

Is there a capacitor in the DEM circuit?
Do you use a buffer between LE/WS and the DEM circuit?

Thank you for any help you can provide

Gary

Hi oshifis,



From the IEEE journal of solid state circuits vol. SC-14, no.3, June 1979 page 553

"The output currents as function of time are shown in Fig. 3(b). The figure shows that the currents with value I have a ripple with the same frequency as the clock generator f, while the current with value 2I has ripple with a frequency f/2".

Practical measurements on all 14 active divider outputs on a number of different TDA1541A DAC chips all showed a ripple frequency of fDEM.

Each active divider output has different step pattern. There are 3 active dividers used for each channel. The DAC output consists of combinations of these binary weighted filtered DC bit currents.

After filtering, the ripple current is low enough to remain inaudible.

On-chip crosstalk occurs, that's why I use the same frequency (44.1 KHz, synchronized) for both DEM oscillator and WS.

 

[ecdesigns]

Hi roger57,

Is there a capacitor in the DEM circuit?

One possible way to synchronize the DEM oscillator with WS is the following:

1.8nF 1% film or NPO cap between pins 16 and 17 (DEM oscillator runs on timing cap).
330nF film cap in series with 22K between WS and pin 16 (synchronization circuit).

Filter cap value (14x) 1uF.

Do you use a buffer between LE/WS and the DEM circuit?

Buffer is not required.

 

[studiostevus]

Hi roger57,

One possible way to synchronize the DEM oscillator with WS is the following:

1.8nF 1% film or NPO cap between pins 16 and 17 (DEM oscillator runs on timing cap).
330nF film cap in series with 22K between WS and pin 16 (synchronization circuit).

Filter cap value (14x) 1uF.

Buffer is not required.

Hi John,
One thing I noticed last night, when I tried to use my DEM synch circuit (simple resistor + diode in series from WS to pin16) on my S1 and S2 chips, that every chip (at least the normal A, S1 and S2 that I have) required different tuning of the signal present on pin16. When I used the normal 'A' chip, I had 12K1 between pin2 and pin16. When I used this setup with the 'S1' chip, I couldn't get a lock. I needed to trim it down to 9K5 to get a lock...

Once I had tuned the resistor to that particular chip, I got good consistent locking of the DEM oscillator to WS. Is that similar in the circuit you describe?

 

[ecdesigns]

Hi studiostevus,

I suggest to try the DEM circuit as described in post #4452.

The signal measured on pin 17 should look very similar to the sawtooth-shaped signals in oscillograms 44k1dem1.jpg and 44k1dem2.jpg I posted earlier.

 

[maxlorenz]

Hi dear -EC-

Somehow the SD card technology is not working for me Not practical and the cards show failures...maybe bad luck...

You mentioned earlier, if memory is correct, the option of direct (isolated) connection to PC with, as I understood, some kind of local RAM to store a lot of music?
Perhaps a PC connection that can ON/OFF would be optimal. Am I wrong?

Thank you,
M.

 

[ecdesigns]

Hi maxlorenz,

Somehow the SD card technology is not working for me  Not practical and the cards show failures...maybe bad luck…

Are you using a QA-550 SD-card player? If yes, have you installed the latest firmware for it?

QLS Electronics Hi-Fi Audio/DAC datasheet download

There are quality differences between SD cards. Some cards are too slow to ensure required throughput resulting in drop-outs.

I personally prefer Kingston class 4, and Platinum class 10, these work excellent with the SD8-transport.

You mentioned earlier, if memory is correct, the option of direct (isolated) connection to PC with, as I understood, some kind of local RAM to store a lot of music?
Perhaps a PC connection that can ON/OFF would be optimal. Am I wrong?

The option of isolated RS232 > USB interface is intended for low speed communications between computer and SD8-transport. This enables the use of a computer-based graphical user interface for the SD8-player. This interface is not intended nor suitable for digital audio streaming

 

[roger57]

Hi John,

The cap to be lifted for testing should be the lowest weighted value in the output so we can observe the minimal initial condition?

Or the highest weighted value so we can see the biggest impact on DEM amplitude reduction as values are tested?

Gary

Hi roger57,



One possible way to synchronize the DEM oscillator with WS is the following:

1.8nF 1% film or NPO cap between pins 16 and 17 (DEM oscillator runs on timing cap).
330nF film cap in series with 22K between WS and pin 16 (synchronization circuit).

Filter cap value (14x) 1uF.



Buffer is not required.

 

[maxlorenz]

Thanks -EC- for the reply nº4456

I do use that reader with the latest updates to firmware.
The main problem I'm having is that the computers don't recognize me as propietor of the cards, after a few uses, no matter what I do. I use Linux (but I am not very skilled with the command line) and Windows.

After a couple of years, I feel again the DIY bite.

Keep on the excellent job.
M.

 

[dady]

Thanks -EC- for the reply nº4456

I do use that reader with the latest updates to firmware.
The main problem I'm having is that the computers don't recognize me as propietor of the cards, after a few uses, no matter what I do. I use Linux (but I am not very skilled with the command line) and Windows.

After a couple of years, I feel again the DIY bite.

Keep on the excellent job.
M.

Hi Mauricio, which distribution of linux do you have?
I use linux from long time and some clues is possible to show you.
Did you install Midnight Commander? Is like commander of windows but powerful and reliable. Try in skype tonight.
Best Max

 

[studiostevus]

Hi studiostevus,

I suggest to try the DEM circuit as described in post #4452.

The signal measured on pin 17 should look very similar to the sawtooth-shaped signals in oscillograms 44k1dem1.jpg and 44k1dem2.jpg I posted earlier.

I will try that one, once I get the required cap values, as:

I noticed that on the S1 (1989) chip, it gets into a locked state, and after a while loses locked state for a couple of minutes, and after a while gets back into locked state. I didn't notice this on the 'normal A' (1998).