I'm starting a new thread to discuss the calculations of SOAs and protection circuits, in regular pushpull class AB designs.
I'm making some calculations but I'm not certain I'm doing this right, so perhaps someone will be able to bring some insights.
First I'd like to make sure I am properly collecting the SOA data from datasheets for use in plotting this curve digitally for comparisons with load lines later.
I think it might be a good tool to use excel to store that data. Such sheets could be posted here for sharing.
At the moment, I am looking at making a graph with collector currents on y axis and the vce on x axis, and although I think I have the y axis right, I'm not sure I'm doing the x axis in the best way, especially if I want to include the load reactance factor.
I also would like to end up with an excel sheet to easily calculate the values of the protection circuit resistors. I would use the leach amp as a model for this. What I am trying to figure out is what are all the parameters to take into account in the calculations for the protection circuit resistors, since there are multiple output devices and there are multiple emitter resistors with protection circuit sensor resistors on each of them, all leading to the protection circuit. This is a little complex and the SOA has to be taken into account for proper protection against shorts but to avoid any adverse effect on the sound. So basically I see the protection circuit action should occur above the clipping point, so the clipping is basically the only source of overload related distortion and not the protection circuit limiting the output power before clipping.
Anyone wants to drop in???
I'm making some calculations but I'm not certain I'm doing this right, so perhaps someone will be able to bring some insights.
First I'd like to make sure I am properly collecting the SOA data from datasheets for use in plotting this curve digitally for comparisons with load lines later.
I think it might be a good tool to use excel to store that data. Such sheets could be posted here for sharing.
At the moment, I am looking at making a graph with collector currents on y axis and the vce on x axis, and although I think I have the y axis right, I'm not sure I'm doing the x axis in the best way, especially if I want to include the load reactance factor.
I also would like to end up with an excel sheet to easily calculate the values of the protection circuit resistors. I would use the leach amp as a model for this. What I am trying to figure out is what are all the parameters to take into account in the calculations for the protection circuit resistors, since there are multiple output devices and there are multiple emitter resistors with protection circuit sensor resistors on each of them, all leading to the protection circuit. This is a little complex and the SOA has to be taken into account for proper protection against shorts but to avoid any adverse effect on the sound. So basically I see the protection circuit action should occur above the clipping point, so the clipping is basically the only source of overload related distortion and not the protection circuit limiting the output power before clipping.
Anyone wants to drop in???
Hi there,
Have a look at the attached excell file.
Page 1: fill in red numbers (there is a lot of extra info: E.g. class A power, standards PSU voltage...)
Page 2: SOA curve from choosen BJT have to copied from datasheet into numbers. (easy is to use start, stop and all knee points from the SOA curve from the datasheet).
Page 3: Tada: you have visual idea whether your OPS is running out off there power rating.
Just play arround with this file a bit, after a while it will become very very convenient.
Cheers.
Have a look at the attached excell file.
Page 1: fill in red numbers (there is a lot of extra info: E.g. class A power, standards PSU voltage...)
Page 2: SOA curve from choosen BJT have to copied from datasheet into numbers. (easy is to use start, stop and all knee points from the SOA curve from the datasheet).
Page 3: Tada: you have visual idea whether your OPS is running out off there power rating.
Just play arround with this file a bit, after a while it will become very very convenient.
Cheers.
Thanks, very interesting. I wasn't thinking about getting into the V-I type of limiter calculations, as it's a little more complex, but since that paper covers this, why not. A simple sloped V-I should be feasible.
Now that's what I'm talking about!!!
I'll take a good look at this. More to share later...
This seems to work great. But I think it needs comments to help in its proper use.
There are non english words and I'm just guessing what they mean.
Is there an automated way to choose the ouput transistors so the soa graph changes accordingly?
I assume the graph shows the load line in a worst case reactive scenario, is that right? What about inductive?
In case an amp is used in an active setup, without any filters between it and the speakers, wouldn't that be an inductive only situation? I guess it doesn't matter if it's reactive or inductive, the result is the same, except the phase is the opposite way.
Hi spookydd,
The output filters should be used to prevent burst local oscillations (EF pair is unstable) to enter the speakers (and this oscillations can permanently damage the tweeters), so they are filtered by the Zobel network and the output coil.
A good choice for output transistors are the MJL21193/MJL21194 pair, they are robust and they can handle large currents, if one pair isn't sufficient you can use more paralleled devices.
Always use base stopper resistors, because they make the output devices less prone to oscillations. You can also use base to collector capacitors or zobels, but personally I think they change phase characteristics too much.
Pay attention also to the predrivers power dissipation.
About SOA I don't know much but I'm thinking in incorporating the circuit of figure 41 of Michael Kiwanuka's paper in my design.
Best regards
Daniel
The output filters should be used to prevent burst local oscillations (EF pair is unstable) to enter the speakers (and this oscillations can permanently damage the tweeters), so they are filtered by the Zobel network and the output coil.
A good choice for output transistors are the MJL21193/MJL21194 pair, they are robust and they can handle large currents, if one pair isn't sufficient you can use more paralleled devices.
Always use base stopper resistors, because they make the output devices less prone to oscillations. You can also use base to collector capacitors or zobels, but personally I think they change phase characteristics too much.
Pay attention also to the predrivers power dissipation.
About SOA I don't know much but I'm thinking in incorporating the circuit of figure 41 of Michael Kiwanuka's paper in my design.
Best regards
Daniel
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SOA is a bit complex, one would think that it's the large signal into low impedances that is the worst, but actually it is a no signal (or almost no signal) into a "short" that is the worst, as the amplifiers output devices then sees the full rail voltage and at the same time it should deliver indefinite current into the short.
This must be the worst case scenario, most devices (BJT') are are around 3-4 Amp at 50 V.
At higher voltage outputs they can handle significantly higher currents as the voltage over the device is lower, So amplifiers very rarely smoke on dynamic loads, but most often at mishandeling and short-circuiting while changing speakers with no signal on the output (apart from the little offset alway present)
I design my overcurrent protection as a simple first order design, and simply add enough devices to get the desired current capability, I know this is not optimising the use of the devices, but this is DIY..
For me the clipping behavior is more important, and carefully executed the protection circuits can make sure that you have a soft rounded clipping with no latching or reverse curving of the signal.
This must be the worst case scenario, most devices (BJT') are are around 3-4 Amp at 50 V.
At higher voltage outputs they can handle significantly higher currents as the voltage over the device is lower, So amplifiers very rarely smoke on dynamic loads, but most often at mishandeling and short-circuiting while changing speakers with no signal on the output (apart from the little offset alway present)
I design my overcurrent protection as a simple first order design, and simply add enough devices to get the desired current capability, I know this is not optimising the use of the devices, but this is DIY..
For me the clipping behavior is more important, and carefully executed the protection circuits can make sure that you have a soft rounded clipping with no latching or reverse curving of the signal.
1: Send me a PM, than I can expain better with some screenshots perhaps.
2: No, you have to copy the SOA data points in the top matrix. Personally the first thing I do when designing a new amp is to choose a certain output device.
3: Yes, the phase angle can be choosen on the left bottom, for each load. I mostly use 65degrees for 8r, 45 for 4R. This looks conservative to me when looking at speaker impedance plots.
4: I have no idea. Personally I design very conservative. I hate VI limiters and put rather a few extra output devices which further helps me to increase classe A power.
This would be easy to calculate, as it ignores all considerations of complex loads and only focuses on the current. This is the way I was doing it until now, but that's not allowing a full use of the SOAs.
Wouldn't the zobel prevent issues while the load is removed from the amp?
As far as plain shorts on the output is concerned, if the calculations are made per SOA, this should take care of it. With the proper number of outputs to handle the sustained short, plus making sure the drivers can also handle it, there shouldn't be any problems.
And how to you handle this? How do you make the clipping as soft rounded???
What do you mean by PM?
What about when the amp is directly connected to a single woofer, in an active configuration (no passive filters)??
In that case, there should be no reactive characteristic and only inductive.
I would think the load could never reach 100% reactive or inductive, so what should we conservatively shoot for?
That is the type of setup that I'm aiming at right now, 4 ways, with each amp directly connected to its own speaker.
I'm trying to use mathcad to draw up SOA charts, but I'm not certain about my formulas. If anyone knows how to use that, I'd like to double check my calculations. But that only checks to make sure the load line sits well within the soa, but doesn't help with the calculation on the protection circuit.
3 pairs MJ15003/4
Here is a snapshot of a plot that I made for a 3 pairs output of MJ15003/4 with rails at 60V and 70V on a load of 8 and 4 ohms. First I aimed at resistive loads and then 100% reactive (using 2 x Vcc).
The colors are:
green: 8ohms at 60V rails resistive. 8ohms 60V rails 100% reactive (2 x Vcc)
orange: 8ohms at 70V rails resistive
brown: 4 ohms at 70V rails resistive
red: 4 ohms at 60V rails resistive
the SOA in black is taken from the MJ15003/4 datasheet, plotted with the knees at:
Ic: 20 20 5 0.5 0.2
Vce: 2 12 50 140 140
The question is on the reactive load line. I just used 2 x Vcc, but I'm not certain I'm using the right formulas.
If I can get all this right, then half the work is done.
Here is a snapshot of a plot that I made for a 3 pairs output of MJ15003/4 with rails at 60V and 70V on a load of 8 and 4 ohms. First I aimed at resistive loads and then 100% reactive (using 2 x Vcc).
The colors are:
green: 8ohms at 60V rails resistive. 8ohms 60V rails 100% reactive (2 x Vcc)
orange: 8ohms at 70V rails resistive
brown: 4 ohms at 70V rails resistive
red: 4 ohms at 60V rails resistive
the SOA in black is taken from the MJ15003/4 datasheet, plotted with the knees at:
Ic: 20 20 5 0.5 0.2
Vce: 2 12 50 140 140
The question is on the reactive load line. I just used 2 x Vcc, but I'm not certain I'm using the right formulas.
If I can get all this right, then half the work is done.
Attachments
To bump the old thread, I have a question regarding SOA given in datasheets.
Take as an example the 2SC4027 datasheet. The SOA includes graphs that seem to specify the maximum, non repetitive (as I understand but this is essentially my question) V-I relationship. For time intervals of 1ms, 10ms, 100ms.
What if you stay well inside the DC SOA, but the power swings momentarily but repetitively to these extreme 1ms SOA limits, but for no more than 1us each time. For example, when driving a high frequency sine into a load. Would then the transistor be in danger, or is it ok as long as DC power falls within the DC safe operating area?
Take as an example the 2SC4027 datasheet. The SOA includes graphs that seem to specify the maximum, non repetitive (as I understand but this is essentially my question) V-I relationship. For time intervals of 1ms, 10ms, 100ms.
What if you stay well inside the DC SOA, but the power swings momentarily but repetitively to these extreme 1ms SOA limits, but for no more than 1us each time. For example, when driving a high frequency sine into a load. Would then the transistor be in danger, or is it ok as long as DC power falls within the DC safe operating area?
I think you'd have to do some thermal modelling to figure out the repetitive ratings, but I reckon you'd need to know the time constant for hot spot diffusion/dispersal to do that, which is presumably tricky to define, let alone measure, as hot spot distribution/spacing may vary from die to die...
For the old legacy Motorola parts, they often have transient thermal impedance plots. From that and pulse width data you would pick off the factor by which you multiply Rth and therefore the temperature rise The derating the appropriate curve on the SOA graph. Unfortunately, most of the stuff they later acquired (in this case from Sanyo) doesnt have this data. Best estimate would be for something with a similar die size. The original versions of that part is the C3902, in a TO-126. So I’d look for a transient thermal curve for something in a TO-126. And be conservative, because it would be an extrapolation.
Many thanks for your answers.
I will see what I can find, for the time being I will make sure that I parallel enough devices so that the peak instantaneous power stays within the DC acceptable limit (I think this is conservative enough).
The 2SC4027 comes in TO-251 package, so I assume I should extrapolate thermal information from such a package. I will also calculate the same stuff for a 2N5401 (TO-92), which is about half the thermal capability in free air, as expected.
Mark Tillotson, would you happen to have a source for introducing me to the hot spot diffusion calculations you mention? I am always happy to dig deep down to the core of a matter.
I will see what I can find, for the time being I will make sure that I parallel enough devices so that the peak instantaneous power stays within the DC acceptable limit (I think this is conservative enough).
The 2SC4027 comes in TO-251 package, so I assume I should extrapolate thermal information from such a package. I will also calculate the same stuff for a 2N5401 (TO-92), which is about half the thermal capability in free air, as expected.
Mark Tillotson, would you happen to have a source for introducing me to the hot spot diffusion calculations you mention? I am always happy to dig deep down to the core of a matter.
The question is what the definition is of non-repetitive. It is non-repetitive if the junction temperature can settle to the stationary value between pulses. One pulse every few seconds can be classified as non-repetitive. Music generally fits this.
Then there is the inductive load from a speaker. With that, the load line can easily intrude within the SOA even if the ohmic I/V curve does not.
Jan
Mark: well I was more or less referring to a physics equation, which I assumed would translate into an electrical analogy of thermal resistances etc . Whatever you please is the answer, you are not obliged to anything!
Jan, I understand your remark. And this is the reason why I posted: I was quite confident that definition of non-repetitive is to let the transistor "recover" thermally from a transient, but in my application, I will supply sinusoidal or pulse waveforms, which means that the repetition rate will be the frequency of the signal.
For example, say you pass a 2.5MHz sine to a load, dissipating an average power of 0.5W at 50oC ambient across a 2SC4027, and that means that every 400ns the power through the device swings between 1W and 0W (assume zero, or near zero idle bias). At 50oC, the maximum DC quoted power is 0.8W. Would it be safe to assume that since the transient's duration is way less than 1ms every time, the only thing that matters is average power? Or is it possible that the transistor will not be able to withstand such a repetitive behavior?
. Whatever you please is the answer, you are not obliged to anything! Jan, I understand your remark. And this is the reason why I posted: I was quite confident that definition of non-repetitive is to let the transistor "recover" thermally from a transient, but in my application, I will supply sinusoidal or pulse waveforms, which means that the repetition rate will be the frequency of the signal.
For example, say you pass a 2.5MHz sine to a load, dissipating an average power of 0.5W at 50oC ambient across a 2SC4027, and that means that every 400ns the power through the device swings between 1W and 0W (assume zero, or near zero idle bias). At 50oC, the maximum DC quoted power is 0.8W. Would it be safe to assume that since the transient's duration is way less than 1ms every time, the only thing that matters is average power? Or is it possible that the transistor will not be able to withstand such a repetitive behavior?
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A very good question to which there is, unfortunately, a rather long answer. As WG said, you need to look at the transient thermal impedance. For short pulses the transistor can handle larger powers - quite significantly - than the DC values. If you haven't got the data, then you need to measure it.
To measure it is complicated. You need to be able to pulse the device with long to short pulses at constant temperature but over a range of temperatures ideally, and measure the instantaneous temperature from interrupting the pulse and measuring Vbe, (at a much reduced current) having calibrated the Vbe against IC and temperature beforehand.Then looking to see how it responds to a pulse. Then have a bit of fun trying to extract the thermal data (R and C equivalents) in the form of a sort of Fourier analysis.
In summary, it's somewhat specialised, but you might get some idea with a basic set of measurements.
However, you can do some estimations on the pulses you plan to use by calculating some equivalent pulses, checking the temperature and extrapolating.
Usually transistor ratings are given for ambient or case temperature. If the device can do a certain power at ambient it can usually dissipate more if the device is cooled in some way such that the junction temperature is not exceeded.
And, usually hotspots don't lead to damage if the offending pulse is very short. For repetitive short pulses I would suggest that the transient response would allow slight overshoots beyond the DC SOA as long as the average temperature and pulse dissipation are apparently within the device temperature limits.
But the only other way to check would be to actually lifetest the device!
To measure it is complicated. You need to be able to pulse the device with long to short pulses at constant temperature but over a range of temperatures ideally, and measure the instantaneous temperature from interrupting the pulse and measuring Vbe, (at a much reduced current) having calibrated the Vbe against IC and temperature beforehand.Then looking to see how it responds to a pulse. Then have a bit of fun trying to extract the thermal data (R and C equivalents) in the form of a sort of Fourier analysis.
In summary, it's somewhat specialised, but you might get some idea with a basic set of measurements.
However, you can do some estimations on the pulses you plan to use by calculating some equivalent pulses, checking the temperature and extrapolating.
Usually transistor ratings are given for ambient or case temperature. If the device can do a certain power at ambient it can usually dissipate more if the device is cooled in some way such that the junction temperature is not exceeded.
And, usually hotspots don't lead to damage if the offending pulse is very short. For repetitive short pulses I would suggest that the transient response would allow slight overshoots beyond the DC SOA as long as the average temperature and pulse dissipation are apparently within the device temperature limits.
But the only other way to check would be to actually lifetest the device!
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