Spice simulation

[x-pro]

Hi Andy,

it is a very interesting paper you've linked in the other thread:

http://www.nsti.org/Nanotech2002/WCM2002/WCM2002-PBendix.pdf

One of good reasons to use EKV model apparently is that it could be much better in simulating unlinear capacitances behaviour of a MOSFET than BSIM3. As you may guess it is the unlinearity of the capacitances that could be crucial in the crossover region of an AB output stage at higher frequencies.

Cheers

Alex

 

[andy_c]

I'm not sure what to make of the capacitance plots. For instance, on pages 56 and 58, both Cgs and Cgd go to zero for Vgs = 0. But the plots of capacitance vs. Vds on the datasheets for the vertical devices are taken with Vgs = 0, and those capacitances sure aren't zero!

I suspect the simulated capacitances are only valid for laterals. My plan for simulating Cgd was to use a subcircuit with an external capacitor. LTSpice allows a "Q=" expression for capacitors, specifying an expression for Q(v) to get nonlinear capacitance behavior. It's pretty clear what to do for Cgd, but Cgs is still a mystery to me. I guess I should get a good capacitance meter and just measure them.

I'd love to see the derivation of those capacitance expressions, done for both lateral and vertical devices - if there is a closed form expression for them. Then I'd have a much better idea of what I should be shooting for.

 

[andy_c]

Here's a link to a MOSFET modeling book. In another thread in a discussion with Alex, I posted a link to a file that was the first chapter of this book. This is the whole book . Link to PDF of book

Lots of goodies in there, including EKV.

 

[Bob Cordell]

I'm not sure what to make of the capacitance plots. For instance, on pages 56 and 58, both Cgs and Cgd go to zero for Vgs = 0. But the plots of capacitance vs. Vds on the datasheets for the vertical devices are taken with Vgs = 0, and those capacitances sure aren't zero!

I suspect the simulated capacitances are only valid for laterals. My plan for simulating Cgd was to use a subcircuit with an external capacitor. LTSpice allows a "Q=" expression for capacitors, specifying an expression for Q(v) to get nonlinear capacitance behavior. It's pretty clear what to do for Cgd, but Cgs is still a mystery to me. I guess I should get a good capacitance meter and just measure them.

I'd love to see the derivation of those capacitance expressions, done for both lateral and vertical devices - if there is a closed form expression for them. Then I'd have a much better idea of what I should be shooting for.

Hi Andy,

Keep up the good work! These improved models are VERY valuable, and I've already gotten some good output stage crossover distortion results using the models of the Toshiba MOSFETs.

I've done some detailed measurements on IRFP240 and 9240 devices, both dc and capacitance. My recollection is that Cgs didn't change very much with Vgs. BTW, people that make assumptions about the behavior of Cgs or Ciss based on the gate charge curve appear to be being very misled. I strongly recommend against drawing conclusions based on the gate charge curves.

Cheers,
Bob

 

[andy_c]

Thanks Bob. All my plans will start to hit the fan tomorrow night I think .

 

[Edmond Stuart]

Re: EKV modeling of power MOSFETs

.........................
Hi Edmond,

I'm not using these devices, but after I'm finished extracting model parameters for the devices I do use, I could try extracting data for these if you're interested in trying them.
.........................

Hi Andy,

So you are currently using other devices. What are they, verticals from Fairchild?
As for modeling 'my' MOSFETs, I'm not in a hurry, so please, look at these devices only if you have enough time. Thanks in advance.

Cheers, Edmond.

PS: Good luck with your 'EKV plug-in'.

 

[PMA]

It would be nice guys if some of you was willing to build the simulated circuits and compare results of measurement with simulation. I have usually used simulation only for preliminary playing with circuit. Now I am comparing THD and CCIF IM results of simulated and measured circuit, the circuit, which is rather simple than complex. The results of simulation and measurement do not fit very well, though some trends and indications of simulation are quite useful. Anyway, if the results are only simulated, they should be assessed with great care.

 

[Edmond Stuart]

It would be nice guys if some of you was willing to build the simulated circuits and compare results of measurement with simulation. I have usually used simulation only for preliminary playing with circuit. Now I am comparing THD and CCIF IM results of simulated and measured circuit, the circuit, which is rather simple than complex. The results of simulation and measurement do not fit very well, though some trends and indications of simulation are quite useful. Anyway, if the results are only simulated, they should be assessed with great care.

Hi Pavel,

Look here for an answer:
http://www.diyaudio.com/forums/showthread.php?s=&postid=1225443#post1225443
BTW, I suppose you do have the real life THD figures of Bob Cordell's EC amp.

Cheers, Edmond.

 

[PMA]

Hi Edmond,

in case that I FIRST measure the amp and THEN simulate, I sometimes get the same results Provided I find appropriate models, corresponding to the measurement. I would rather prefer to be able to predict the real results, then to verify them by modified simulation

 

[andy_c]

Re: Re: EKV modeling of power MOSFETs

So you are currently using other devices. What are they, verticals from Fairchild?

Hi Edmond,

The MOSFETs I am using are:

Output stage:
N-channel: IRF/Vishay IRFP244
P-channel: Fairchild FQA9P25

Driver/VAS cascode/VAS buffer:
N-channel: Fairchild FQP3N25
P-channel: Fairchild FQP2P25

PS: Good luck with your 'EKV plug-in'.

Thanks! I"m having some trouble at the moment. I have the function coded and returning results, and I tried the example from the book I linked in this post (figure 7.3 of the book). The data from LTSpice agrees with figure 7.3 in the book, but my code is about 20 percent off for the current at Vds = 5V. I've checked the code against the equations in the manual several times now, and can't find any discrepancies.

I've put in a request for the Verilog-A source code for the model, but haven't received a reply yet. Hopefully they will respond soon. What I plan to do is run the Verilog-A through a tool called ADMS, which will output C code. If that code is readable, I'll compare it with my VBA code and make any changes as necessary.

 

[Edmond Stuart]

Hi Edmond,

in case that I FIRST measure the amp and THEN simulate, I sometimes get the same results Provided I find appropriate models, corresponding to the measurement. I would rather prefer to be able to predict the real results, then to verify them by modified simulation

Hi Pavel,

I understand perfectly well what you mean, but I can assure you I didn't fiddle with the models; of each involved tranny I have just one model.
Actually, just as Bob Cordell, I was rather amazed that the spiced THD was so well in accordance with his measurements.

Cheers, Edmond.

 

[PMA]

Hi Edmond,

in this case you have achieved excellent result!

Regards,
Pavel

 

[andy_c]

Re: Re: EKV modeling of power MOSFETs

As for modeling 'my' MOSFETs, I'm not in a hurry, so please, look at these devices only if you have enough time. Thanks in advance.

Hi Edmond,

I've thought about this some more, and realized it might be a good idea to do the 2SJ201 and 2SK1530 first. I noticed you have some data for these in weak inversion. Also, if you'd be willing to review the results and method of the extraction and suggest possible improvements in the procedure, I could get these improvements incorporated into the spreadsheet. I could try different ideas until we're both happy with the results for these devices. Then parameter extraction for all further devices could make use of these improvements.

I'd also like to find out if Micro-Cap has a facility for nonlinear capacitors beyond the use of POLY in the capacitance expression. This would avoid having to use a diode from gate to drain, which is not part of the device physics. For example, LTSpice allows specifying a capacitor value as "Q=expression" to get a nonlinear Q-V characteristic. With that technique, I could use the same nonlinear capacitance expression for Cgd that the LTSpice VDMOS model uses.

The EKV guys from Switzerland did not respond yet, but I found the Verilog-A code for EKV 2.6 on a web site. The results of SPICE simulation and the VBA function are much closer now. It turns out the interpolation function in the Verilog-A code is different from what's in the EKV paper. Still, there are some small differences in the data.

Could you try this simple DC biasing test circuit in Micro-Cap? I've attached the model file. The configuration is as follows:

Body = source = ground
Gate = 0.7 Volts
Drain = 5 Volts

FET dimensions: L = 0.5u. W = 10u
These dimensions are not in the model file, as LTSpice gives an error when that's done. This example is from chapter 7 in the book I linked to earlier.

I'm getting a drain current of 10.79 uA with LTSpice, and 10.30 uA with the VBA code. According to the EKV web site, EKV 2.6 is level 44 in Micro-Cap. Thanks in advance if you'd be willing to try this.

 

[PMA]

Hi Andy,
----------------
Capacitance equations
Meyer model for gate capacitance
Levels 1-3 use the capacitance model proposed by Meyer. The charges are modeled
by three nonlinear capacitances, Cgb, Cgd, and Cgs.
Cox = COX • W • Leff
Accumulation region (Vgs < Von - PHI)
For Vgs < Von - PHI,
Cgb = Cox + CGBO • Leff
Cgs = CGSO • W
Cgd = CGDO • W
Depletion region (Von - PHI < Vgs < Von)
Cgb = Cox • (Von - Vgs)/PHI + CGBO • Leff
Cgs = 2/3 • Cox • ((Von - Vgs)/PHI + 1) + CGSO • W
Cgd = CGDO • W
Saturation region (Von < Vgs < Von + Vds)
Cgb = CGBO • Leff
Cgs = 2/3 • Cox + CGSO • W
Cgd = CGDO • W
Linear region:
For Vgs > Von + Vds,
Cgb = CGBO • Leff
Cgs = Cox • (1 - ((Vgs - Vds - Von)/(2•(Vgs - Von) - Vds))2) + CGSO • W
Cgd = Cox • (1 - ((Vgs - Von)/(2•(Vgs - Von) - Vds))2) + CGDO • W
Junction capacitance
If CBS=0 and CBD=0 then
Cbs = CJ(T)•AS•f1(VBS) + CJSW(T)•PS•f2(VBS) + TT•GBS
Cbd = CJ(T)•AD•f1(VBD) + CJSW(T)•PD•f2(VBD) + TT•GBD
else
Cbs = CBS(T)•f1(VBS) + CJSW(T)•PS•f2(VBS) + TT•GBS
Cbd = CBD(T)•f1(VBD) + CJSW(T)•PD•f2(VBD) + TT•GBD
GBS= DC bulk-source conductance = d(IBS)/d(VBS)
GBD= DC bulk-drain conductance = d(IBD)/d(VBD)
-----------------------
(in profi MC version)

Regards,
Pavel

 

[Edmond Stuart]

Re: Re: Re: EKV modeling of power MOSFETs

Hi Edmond,

I've thought about this some more, and realized it might be a good idea to do the 2SJ201 and 2SK1530 first.

I have no objection to that.

I noticed you have some data for these in weak inversion. Also, if you'd be willing to review the results and method of the extraction and suggest possible improvements in the procedure,

Of course I'm willing to do that.

I could get these improvements incorporated into the spreadsheet. I could try different ideas until we're both happy with the results for these devices. Then parameter extraction for all further devices could make use of these improvements.

Good idea.

I'd also like to find out if Micro-Cap has a facility for nonlinear capacitors beyond the use of POLY in the capacitance expression. This would avoid having to use a diode from gate to drain, which is not part of the device physics. For example, LTSpice allows specifying a capacitor value as "Q=expression" to get a nonlinear Q-V characteristic. With that technique, I could use the same nonlinear capacitance expression for Cgd that the LTSpice VDMOS model uses.

The help file of Micro-Cap says:

" Ex1. A typical nonlinear junction capacitance can be given the expression:
2pF/((1-V(p,n)/.7)**.5)
where V(p,n) is the voltage between nodes 'n' and 'p'.

Ex2. A time dependent capacitor can be given the expression:
5.0pF*(1+2e-6*T) "

As you see, these techniques are not only possible in LTSpice but also in Micro-Cap.

The EKV guys from Switzerland did not respond yet, but I found the Verilog-A code for EKV 2.6 on a web site. The results of SPICE simulation and the VBA function are much closer now. It turns out the interpolation function in the Verilog-A code is different from what's in the EKV paper. Still, there are some small differences in the data.

Hmm... Anyhow, any idea how the interpolation is done, by means of cubic splines, B-splines, polynomial interpolation?

Could you try this simple DC biasing test circuit in Micro-Cap? I've attached the model file. The configuration is as follows:

Body = source = ground
Gate = 0.7 Volts
Drain = 5 Volts

FET dimensions: L = 0.5u. W = 10u
These dimensions are not in the model file, as LTSpice gives an error when that's done. This example is from chapter 7 in the book I linked to earlier.

I'm getting a drain current of 10.79 uA with LTSpice, and 10.30 uA with the VBA code. According to the EKV web site, EKV 2.6 is level 44 in Micro-Cap. Thanks in advance if you'd be willing to try this.

Okay. Although I've never played with EKV models before, I'll try that, the more so as I'm also curious about the results.

Cheers, Edmond.

 

[Edmond Stuart]

Re: Re: Re: EKV modeling of power MOSFETs

.................
I'm getting a drain current of 10.79 uA with LTSpice, and 10.30 uA with the VBA code. According to the EKV web site, EKV 2.6 is level 44 in Micro-Cap. Thanks in advance if you'd be willing to try this.

Hi Andy,

I'm getting 10.795uA. As you see, a gross discrepancy

If I set EKVINT = 1, then I'm getting 9.162uA. According to the manual this option select a different interpolation method: F(v) = ln^2(1+exp(v/2)). However, the manual says nothing about the default interpolation formula.

BTW, the Id/Vgs doesn't resemble a power MOSFET, rather an extreme small signal tranny. Is that correct?

Cheers, Edmond.

 

[andy_c]

Hi Andy,
----------------
Capacitance equations
Meyer model for gate capacitance

Thanks for that info, Pavel.

 

[andy_c]

Re: Re: Re: Re: EKV modeling of power MOSFETs

Hi Andy,

I'm getting 10.795uA. As you see, a gross discrepancy

Thanks for trying this out.

Looks like LTSpice and Micro-Cap are really close here. The current reported by LTSpice is 10.7944 uA. I'd love to get the VBA code that close.

If I set EKVINT = 1, then I'm getting 9.162uA. According to the manual this option select a different interpolation method: F(v) = ln^2(1+exp(v/2)). However, the manual says nothing about the default interpolation formula.

Hmmm. When I use this interpolation function I get 8.69 uA. So it's not just the interpolation function that's causing the discrepancy.

BTW, the Id/Vgs doesn't resemble a power MOSFET, rather an extreme small signal tranny. Is that correct?

Yes, it's a small device taken from the EKV chapter (chapter 7) in the book I linked to in this post. The author is using AIM Spice, and it looks like he is getting just a bit less than 11 uA also.

My complete tale of woe on this subject can be found in the newsgroup sci.electronics.cad.

 

[PB2]

Andy, is this the Verilog-A code that you used, just to be sure I'm looking at the same thing:
http://legwww.epfl.ch/ekv/verilog-a/

Pete B.

 

[andy_c]

Andy, is this the Verilog-A code that you used, just to be sure I'm looking at the same thing:
http://legwww.epfl.ch/ekv/verilog-a/

That's a simplified version of the actual code. I'm not sure why they put that there. I've attached the Verilog code I downloaded to this message. The interpolation function of the actual code looks buggy. Notice the if the first "if" statement evaluates to true, it will be overwritten in the "else" of the next "if" statement.

// Forward current (43-44)
fv=(VP-VS)/$vt;

if (fv >= -0.35)
z0=2.0/(1.3 + fv - ln(fv+1.6));

if (fv>=-15 && fv<-0.35)
z0= 1.55 + exp(-fv);
else
z0=1;

z1=(2.0 + z0) / (1.0 + fv + ln(z0));

if (fv > -15.0)
y=(1.0 + fv + ln(z1)) / (2.0 + z1);
else
y= 1.0 / (2.0 + exp(-fv));

iff = y*(1.0 + y);

I can't seem to get indenting to work.