The diyAudio archives are filled with examples of how not to do things. Guido Tent’s Tube DAC is a case study of how not to distribute a clock. (The schematics presented here were clipped and cropped from schematics of the original design as redrawn by Algar_emi.)
Clip 1
The output of the VCXO, U10, is buffered by U18A and then fanned out with four more gates in U18. The sixth gate in U18 inverts one of the fan-outs. This arrangement was standard practice with TTL logic but it is not good practice with CMOS logic.
As the low-to-high or high-to-low clock transition passes through U18A, the current drawn by the gate causes VCC to dip and GND to spike. This is called ground bounce. It is a fact of life that happens inside the chip. Bypass capacitors, series resistors, ferrites, and inductors will not make it go away.
When the inverted clock transition is leaving U18A and entering U18B, D, E, and F, VCC and GND (inside the chip) are unsettled. The reduced VCC-to-GND differential slows the transition and propagation time of the gates, and that increases jitter. Because the individual gates in the chip are not matched, the changing VCC-to-GND differential will affect the trigger point of each gate differently, thereby increasing clock skew and jitter. With four gates changing nearly simultaneously, the effects of ground bounce increase fourfold and negatively impact the performance gate U18C (/RC_CLK).
Clip 2
At first glance, the circuit formed by U5 and U4 looks like a clever reclocking scheme utilizing feedback; but looks are deceiving. The circuit doesn’t do anything except add noise and make the design look more sophisticated than it actually is. Within two clocks after power-on, the D input of Q4A is always high before every clock and the /Q output becomes a steady state zero. As a result, CLK is just inverted /RC_CLK.
Clip 3
How does inverting the output of the VCXO three times in the noisy confines of U18 and once more in the noisy confines of U5 reduce jitter and improve the quality of the bit clock?
Clip 1
The output of the VCXO, U10, is buffered by U18A and then fanned out with four more gates in U18. The sixth gate in U18 inverts one of the fan-outs. This arrangement was standard practice with TTL logic but it is not good practice with CMOS logic.
As the low-to-high or high-to-low clock transition passes through U18A, the current drawn by the gate causes VCC to dip and GND to spike. This is called ground bounce. It is a fact of life that happens inside the chip. Bypass capacitors, series resistors, ferrites, and inductors will not make it go away.
When the inverted clock transition is leaving U18A and entering U18B, D, E, and F, VCC and GND (inside the chip) are unsettled. The reduced VCC-to-GND differential slows the transition and propagation time of the gates, and that increases jitter. Because the individual gates in the chip are not matched, the changing VCC-to-GND differential will affect the trigger point of each gate differently, thereby increasing clock skew and jitter. With four gates changing nearly simultaneously, the effects of ground bounce increase fourfold and negatively impact the performance gate U18C (/RC_CLK).
Clip 2
At first glance, the circuit formed by U5 and U4 looks like a clever reclocking scheme utilizing feedback; but looks are deceiving. The circuit doesn’t do anything except add noise and make the design look more sophisticated than it actually is. Within two clocks after power-on, the D input of Q4A is always high before every clock and the /Q output becomes a steady state zero. As a result, CLK is just inverted /RC_CLK.
Clip 3
How does inverting the output of the VCXO three times in the noisy confines of U18 and once more in the noisy confines of U5 reduce jitter and improve the quality of the bit clock?
Ulas said:
Until told otherwise by the designer, I remain convinced that the circuit is incorrectly drawn.
While the original schematics is indeed incorrectly drawn, I can confirm that the contents of clip2 are conforming reality, or at least the printed circuit version in my posession.
Ciao, George
Ciao, George
As drawn in Clip 2, the output signal is directly clocked by the input clock, and that has to mean that the circuit's operation is completely different depending on whether the (jittery) audio data arrives before or after the clock edge. Unless the clock has been deliberately delayed (and without jitter), that means distortion.
I think U4 & U5 does not have anything to do with feedback & reclocking.
It is simply a way of enabling / disabling R_clk in function of the presence / missing of a burst type BCKO...
Ciao, George
Ps.: and by the way BCKO is only of secondary importance in the PCM63.
Joseph K said:
Please expalin how a presence / missing BCKO burst comes about. The two inputs to the S/R are RC_CLK and BCKO. Both are derived from the VCXO. RTFM
I know that, but to a clockmonger, jitter is all-important. According to Guido, jitter passes through the substrate of the ICs and permeates every signal. That's why he reclocks everything including the data lines. Even if he wanted to stop CLK for this imaginary BCKO burst, why does he invert it four times? BCKO contains no state information and BCKO is the same as CLK except it has a different jitter spectrum. Maybe the purpose of U4 and U5 is to introduce anti-jitter.
It is most likely that the diagram is in error and as such it seems a mite churlish to ignore this in order to lambast your bete noir of the week.
BCKO is not derived from the VCXO. It is derived from the SM5842.
BCKO is not derived from the VCXO. It is derived from the SM5842.
rfbrw said:
The schematics I posted depict the same components and nets as the originals. The only differences are cosmetic. Knowing how much you all want to get me, don't you think I would have made sure my case was airtight?
In your rush to defend Guido, you are ignoring Joseph K who verified that my schematic matched his Tube DAC PCB!!!!
Read the datasheet. VCXO->RF_CLK->XTI->BCKO. If BCKO isn't derived from the VCXO, where does it come from?
I think Guido’s Tube DAC was originally intended as a joke but nobody got it. In fact, everyone took it so seriously that Guido and his buddies had little choice but to keep it going. Here are the clues:
1) The project description, written by Marc Heijligers, MSEE, reads like a parody.
2) The original schematics obfuscate the U4/U5 no-op by using AND symbols instead of NOR symbols for the 74HC02. I have called this “error” to Guido’s attention, as have others, but he has not changed the schematics. (I used clips from Algar_emi’s schematics because he used the correct symbols, which make clear what the circuit does.)
3) Nothing in the Tube DAC design conforms to Guido’s anti-jitter manifesto. It has no pico gates; it uses multiple gates in a chip; it has a 4-layed PCB, which, most likely, has a VCC plane; it doesn’t use a snake-oil oscillator or magic VCXO; etc.
4) While the U4/U5 red herring is very clever, the rest of the circuit is crude. There are multiple/redundant inversions in important clocks, like /RC_CLK, which reclocks WCKO, the one and only signal that influences jitter in the D-to-A conversion. The reclocking occurs very close to the falling edge of BCKO, which is when WCKO, DOL, & DOR are changing. It would have been more prudent to reclock near the rising edge of BCKO, when everything is stable, and then invert the bit clock to restore the proper phase relationship before sending it to the PCM63s.
5) The project description says, "A special circuit in-between the filter and the DAC chips is used, to reclock all digital signals entering the DAC chips. This reclocking circuit is described elsewhere (clock regeneration and jitter)." but the promised description is nowhere to be found.
6) It is very unusual for an audio product to remain unchanged for six years especially after all its major components are no longer available.
But let’s give Guido the benefit of doubt. It’s possible that when the TubeDAC was finished in 2000, he didn’t know about ground bounce and hadn’t yet developed his anti-jitter manifesto. The former is unlikely because Marc Heijligers, MSEE, talks about ground bounce in the project intro.
If Guido’s manifesto is based on knowledge and experience gained since 2000, why hasn’t he updated the Tube DAC to incorporate his newfound knowledge and experience? Don’t his paying customers deserve it? Well, not if the cost of updating the design would diminish the income he receives from the 6-year old hoax. His idea of an update is to offer the same old PCB with gold-plated traces.
1) The project description, written by Marc Heijligers, MSEE, reads like a parody.
2) The original schematics obfuscate the U4/U5 no-op by using AND symbols instead of NOR symbols for the 74HC02. I have called this “error” to Guido’s attention, as have others, but he has not changed the schematics. (I used clips from Algar_emi’s schematics because he used the correct symbols, which make clear what the circuit does.)
3) Nothing in the Tube DAC design conforms to Guido’s anti-jitter manifesto. It has no pico gates; it uses multiple gates in a chip; it has a 4-layed PCB, which, most likely, has a VCC plane; it doesn’t use a snake-oil oscillator or magic VCXO; etc.
4) While the U4/U5 red herring is very clever, the rest of the circuit is crude. There are multiple/redundant inversions in important clocks, like /RC_CLK, which reclocks WCKO, the one and only signal that influences jitter in the D-to-A conversion. The reclocking occurs very close to the falling edge of BCKO, which is when WCKO, DOL, & DOR are changing. It would have been more prudent to reclock near the rising edge of BCKO, when everything is stable, and then invert the bit clock to restore the proper phase relationship before sending it to the PCM63s.
5) The project description says, "A special circuit in-between the filter and the DAC chips is used, to reclock all digital signals entering the DAC chips. This reclocking circuit is described elsewhere (clock regeneration and jitter)." but the promised description is nowhere to be found.
6) It is very unusual for an audio product to remain unchanged for six years especially after all its major components are no longer available.
But let’s give Guido the benefit of doubt. It’s possible that when the TubeDAC was finished in 2000, he didn’t know about ground bounce and hadn’t yet developed his anti-jitter manifesto. The former is unlikely because Marc Heijligers, MSEE, talks about ground bounce in the project intro.
If Guido’s manifesto is based on knowledge and experience gained since 2000, why hasn’t he updated the Tube DAC to incorporate his newfound knowledge and experience? Don’t his paying customers deserve it? Well, not if the cost of updating the design would diminish the income he receives from the 6-year old hoax. His idea of an update is to offer the same old PCB with gold-plated traces.
Ulas said:
Don't be a nudnik, Ulas. You know as well as I do BCKO aka CLK B comes from the SM5842. And you are also no doubt aware of idea that the inside of a digital filter is a hostile place for clocks. If you accept this idea, reclocking any clocks generated there is the next logical step.
Hi guys!
I read in other threads Guido is developing a new dac.
The new product will not be free, but totally commercial (not only pcbs).
I think Guido didn't share his studies and circuit improvements because he's using them in new dac circuit.
He's in business so he earn from daily working, he's free not to share it (with sharks too!!).
I'm not happy about it... I would really like to learn from the results of Guido experiments!
rfbrw said:
Who said anything about reclocking? CLK_B is not reclocked. If you think it is, you obviously don't understand the circuit. CLK_B and RC_CLK are the only inputs to the circuit composed of U5A, B, and U4A. Both signals are derived from the VCXO, and as such, they have the same frequency and a fixed phase relationship with each other. Whatever their state on one rising edge of RC_CLK, it will be the same on the next, and the next, and the next. Therefore, after the first clock, U4A will never change state. There is no probably circumstance (not even jitter) that would create a phase shift large enough to cause U4A to change state.
If the state of U4A is fixed such that /Q is high, then CLK is permanently low and that’s not a good thing. If /Q is permanently low, then CLK is inverted /RC_CLK. If this is not clear to you, I suggest you get datasheets for the 74HC02 and 74HC74 and study them. Then draw truth tables of all the possible input and output permutations of this circuit.
Don’t feel bad, even Guido Tent doesn’t understand this circuit and he helped create it.
Ulas,
U4A DOES change state.
It's not an argument, it's a fact. And it's a working circuit.
Ciao, George
U4A DOES change state.
It's not an argument, it's a fact. And it's a working circuit.
Ciao, George
For CKSLN=LOW the data work length is 32 bits.
Output is set to 20 bit (table5 in the NPC datasheet seems to be wrong, compare with pin description
).
So BCKO (CLK_B) only changes state for those 20 bits, and is low for the rest of the time (figure9 shows 24 bits in the NPC datasheet)
So U4/U5 could be there to generate a CLK if CKL_B goes low ??
Think the "reclock" block of the block diagram is only U3 and U5C.
Makes sense?
PS, i'm not G.Tent
Output is set to 20 bit (table5 in the NPC datasheet seems to be wrong, compare with pin description
).So BCKO (CLK_B) only changes state for those 20 bits, and is low for the rest of the time (figure9 shows 24 bits in the NPC datasheet)
So U4/U5 could be there to generate a CLK if CKL_B goes low ??
Think the "reclock" block of the block diagram is only U3 and U5C.
Makes sense?
PS, i'm not G.Tent
guido,
hehe 😉
with a small correction:
http://www.diyhifi.org/forums/viewtopic.php?p=12993#12993
Ciao, George
hehe 😉
with a small correction:
http://www.diyhifi.org/forums/viewtopic.php?p=12993#12993
Ciao, George
Ulas said:
As I said much earlier in this thread, I think the circuit, as drawn, is wrong because it effectively shuts off CLK B. I was pointing out what I think it is supposed to do and that is do for CLK B what the 74HC175 does for the other three signals.
Ulas, you seem to be missing the obvious. As drawn, the circuit effectively shuts off CLK_B. No CLK_B, no data loaded into the PCM63's. If this were so all the Tentdacs out there would not work. Clearly this is not the case.
Joseph K said:
Ah, got it i think. The arrangement passes/blocks the masterclock when bck changes state/is low.
Did no go into the details, just thought it had to do with the first sentence in the pcm63 datasheet in the "stopped clock operation section": "normally operated with a continues clock"
But this dac doesn't seem to be normal😀
guido said:
Ah, got it i think. The arrangement passes/blocks the masterclock when bck changes state/is low.
Did no go into the details, just thought it had to do with the first sentence in the pcm63 datasheet in the "stopped clock operation section": "normally operated with a continues clock"
But this dac doesn't seem to be normal😀
Which is why I say clip2 is wrong, A new version of BCKO,CLK_B call it what you will, is created using /RC_CLK. This new regenerated version of CLK_B cannot be gated off by an or gate.
BTW, stopped operation is only supported by the dac. It is actually a function of the digital filter.
Rfbrw,
Wait a minute! That is a NOR gate! And as such, why not could work?
By the way, I had cross - checked again the circuit. I feel forced to say again: it is exactly the same as depicted in the the Clips. And functional..
Though not without some twists..
Ciao, George
Wait a minute! That is a NOR gate! And as such, why not could work?
By the way, I had cross - checked again the circuit. I feel forced to say again: it is exactly the same as depicted in the the Clips. And functional..
Though not without some twists..
Ciao, George
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