Indeed it is a NOR gate. The little dot is there. Might as well just build the thing and see one way or the other.
Having built the circuit, I can now say only one thing. A large portion of humble pie, please Mr Tent. As I write this, the subject of Experiment Number Six is dying and there are 18 clock pulses on the 'scope.
Note to self. Next time you see a SR flip-flop, accept it for what is and move on.
Note to self. Next time you see a SR flip-flop, accept it for what is and move on.
Hm, yesterday I counted 20 pulses on the scope.. 😀
Otherways I'm happy, started to feel alone.
Ciao, George
Otherways I'm happy, started to feel alone.
Ciao, George
so after talking so much about HOW NOT TO DO IT, does anybody here have a clue about HOW TO DO IT? 🙂
I stand corrected. I didn’t notice that the SM5842 used stopped-clock operation. Sorry guys, I should have been more careful.
My previous criticism still stands. Using multiple gates in a HC04 to fanout a clock is a bad idea, especially if you are concerned about jitter. A better way is to use clock driver, which has one input, multiple outputs (some drivers have complementary outputs), and often, multiple VCC and GND pins. Most clock driver chips are individually tested and guaranteed to meet maximum and minimum propagation delay and all other operational parameters including: clock-to-clock skew (jitter), gate-to-gate skew, and package-to-package skew. Anyone who is serious about clocks knows minimum specs are as important as maximums.
The outputs of the SM5842 (BCKO, WCKO, DOL, & DOR) have TTL levels. Minimum VOH is 2.5V. They are driving CMOS gates, which typically have a minimum VIH of 3.15V. This combination is a bad idea. The fact the circuit works is a testament to the fact that most ICs perform much better than their minimum specs, but that is not always the case. It is better to use CMOS gates with TTL-level inputs.
The inputs of the PCM63 have TTL levels. Minimum VIH is 2.4V. They are driven by CMOS gates, which typically have a VOH over 4V. While this combination is not bad, per se, it is preferable to use CMOS gates with TTL-level outputs to drive the DAC chips.
Series resistors are rarely used in high performance, clocked circuits anymore. When CMOS logic first appeared, it was slow and didn’t have enough drive to interface with TTL, the dominant logic family at the time. For CMOS to be accepted, it had to be able to replace TTL logic in existing designs. AC was one of the first CMOS logic families to match TTL in terms of speed and drive but its output signal transitions are brutal. Series resistors are a way to tame the output of AC and related CMOS families. Some CMOS logic families from that time even have series resistors in the chip.
Once CMOS replaced TTL, there was little need for high current drive in CMOS-to-CMOS connections and modern CMOS logic families have more benign output signal transitions. In situations where reflections, ringing, over-shoot, or bounce are a concern, passive or active termination is preferred.
While I misjudged the function of U4/U5, its implementation still leaves a lot to be desired. One of the fundamental rules of clocked circuits is:
The falling edge of /RC_CLK is delayed from the raising edge of RC_CLK by one inverter gate. The raising/falling edge of /Q is delayed from the raising edge of RC_CLK by one flip/flop. It’s hard to know which one will get to the NOR gate first. One can make a guess based on typical propagation delays but there is no guarantee. The staggered arrival times may even cause a glitch in CLK. Here is a timing diagram.
The whole reclocking business can be simplified using a clock driver, one inverter gate, and two latches. Latch BCKO on the falling edge of the clock and latch WCKO, DOL, and DOR on the rising edge. Use latches that have TTL-level inputs and outputs.
Guido Tent is one of the diyAudio Experts who says I don’t know what I’m talking about. When it comes to digital circuit design, Guido Tent doesn’t know what he’s doing.
My previous criticism still stands. Using multiple gates in a HC04 to fanout a clock is a bad idea, especially if you are concerned about jitter. A better way is to use clock driver, which has one input, multiple outputs (some drivers have complementary outputs), and often, multiple VCC and GND pins. Most clock driver chips are individually tested and guaranteed to meet maximum and minimum propagation delay and all other operational parameters including: clock-to-clock skew (jitter), gate-to-gate skew, and package-to-package skew. Anyone who is serious about clocks knows minimum specs are as important as maximums.
The outputs of the SM5842 (BCKO, WCKO, DOL, & DOR) have TTL levels. Minimum VOH is 2.5V. They are driving CMOS gates, which typically have a minimum VIH of 3.15V. This combination is a bad idea. The fact the circuit works is a testament to the fact that most ICs perform much better than their minimum specs, but that is not always the case. It is better to use CMOS gates with TTL-level inputs.
The inputs of the PCM63 have TTL levels. Minimum VIH is 2.4V. They are driven by CMOS gates, which typically have a VOH over 4V. While this combination is not bad, per se, it is preferable to use CMOS gates with TTL-level outputs to drive the DAC chips.
Series resistors are rarely used in high performance, clocked circuits anymore. When CMOS logic first appeared, it was slow and didn’t have enough drive to interface with TTL, the dominant logic family at the time. For CMOS to be accepted, it had to be able to replace TTL logic in existing designs. AC was one of the first CMOS logic families to match TTL in terms of speed and drive but its output signal transitions are brutal. Series resistors are a way to tame the output of AC and related CMOS families. Some CMOS logic families from that time even have series resistors in the chip.
Once CMOS replaced TTL, there was little need for high current drive in CMOS-to-CMOS connections and modern CMOS logic families have more benign output signal transitions. In situations where reflections, ringing, over-shoot, or bounce are a concern, passive or active termination is preferred.
While I misjudged the function of U4/U5, its implementation still leaves a lot to be desired. One of the fundamental rules of clocked circuits is:
The falling edge of /RC_CLK is delayed from the raising edge of RC_CLK by one inverter gate. The raising/falling edge of /Q is delayed from the raising edge of RC_CLK by one flip/flop. It’s hard to know which one will get to the NOR gate first. One can make a guess based on typical propagation delays but there is no guarantee. The staggered arrival times may even cause a glitch in CLK. Here is a timing diagram.
The whole reclocking business can be simplified using a clock driver, one inverter gate, and two latches. Latch BCKO on the falling edge of the clock and latch WCKO, DOL, and DOR on the rising edge. Use latches that have TTL-level inputs and outputs.
Guido Tent is one of the diyAudio Experts who says I don’t know what I’m talking about. When it comes to digital circuit design, Guido Tent doesn’t know what he’s doing.
Let's dispense with personal shots and keep it to the technical stuff.
Ulas said:
Does he claim to be a diyAudio Expert himself, or did you give him that status? Well, since you're the man, make us a good circuit then.
Regards,
Ray.
Joseph K said:
It would been 20 if I had used the PCM1702 or PCM63. I didn't. I used the 18bit AD1868 and the SM5843A.
It is good to critisize, people learn something. Some might even start modding the thing. But using this dac to say this is a bit far fetched:
It was designed long ago (1994-2000) by four people. To quote the project description "We didn’t have any technical backgrounds w.r.t. DAC design initially". People learn.
Start picking on his new dac: no dig filter, no oversampling
🙂 or 🙁 depending on your beliefs 😀
guido said:
The Tube DAC team was headed by a MSEE and they labored for FIVE years. In that five years why didn't anyone of them read a book on clocked circuit design or an appnote on ground bounce? After five years they should have developed a modicum of technical proficiency. Heck, starting with just a high school diploma I progressed from computer operator to system programmer in two years. In five years I was a full-fledged computer engineer and project leader. A year later I was running my own consulting company in Silicon Valley.
If you’ve spent any time in this forum you have probably come across one of Guido Tent’s rants that make up the Clockmonger Manifesto. One of them goes like this: Never use a higher bandwidth then strictly necessary. Jocko Homo says the same thing. In a nutshell, it means don’t use a fast IC when a slower one will do the job. Good advice (although one clockmonger, who has since fallen from grace, says VHC sounds better than HC) and everyone agrees that AC logic should be avoided like the plague.
Embarrassed by my recent faux pas, I was reexamining the Tube DAC schematics to see if there was something else I missed. And yes, I had missed something. U4 is specified as a 74AC74. Why was that? All the other chips are 74HC so why does U4 need higher bandwidth than necessary? It seems the DAC team was hit by the GLITCH. In my previous post I only speculated about the possibility of the GLITCH because I know bad engineering when I see it.
A responsible engineer, when confronted with the GLITCH, would try to understand the root cause and fix it. A mediocre engineer simply applies a Band-Aid and hopes the problem goes away. Guido’s team used the Band-Aid approach. A faster flipflop would increase the chances the rising edge of /Q got to the NOR gate before the falling edge of /RC_CLK and avoid the GLITCH.
Let that be a lesson for you: Any signal that passes through combinatorial logic is not a clock.
Actually, that’s the second rule of clocked circuits, as I learned them. The first is:
That means; don’t mess with a clock. Don’t modify it or tweak it and certainly don’t reclock it. If the timing of a “clock” is so bad that it needs to be reclocked, than it wasn’t a clock in the first place, it was a strobe. Reclocking a strobe doesn’t make a clock; it just makes another strobe.
When Guido Tent describes his soon-to-be-released new DAC with all the reclocking he does, I just laugh. It’s too bad he never learned the basics of clocked circuit design.
Ulas said:
As we say here in Australia, Ulas, you are a legend... in you're
own lunchtime 🙂
Ulas,
I suggest you pull your head in. Constructive criticism here
with clear technical backing is welcomed and can only benefit us.
Destructive criticism with personal attack such as yours really
serves no purpose. You should know better.
Maybe your digital design skills are good, but certainly your people skills are a long way off.
Cheers,
Terry
Ulas is talking.... again....
http://www.diyaudio.com/forums/showthread.php?postid=732828#post732828
http://www.diyaudio.com/forums/showthread.php?postid=732828#post732828
Ulas said:
dear all,
I feel the need to react on some issues, not at all do I need to defend.
the DAC design started because we weren't happy with existing DACs. We worked one evening every 2 weeks during about 5 years, and yes, none of all had specific experience in that area, but we learned
The schematics as on the web do work, the boards are made based on these and hundreds are sols - they all work.
On the clock distribution: A modification has been made to avoid most inverters, this modis not published on the web, but most if not all customers do know about it. the effect by the way was very subtle, the induced jitter of an inverter is not that high, when care has been taken on layout and power supply.
The AC74 is used because it is faster, we needed that because of timing issues. It is deliberately chosen as a solution, and works in all DACs, over all temperature ranges. We could have chosen other solutions, making the circuit much more complex. there is the trade off.
I know not to mess with a clock, but when wanting to drive reclockers, the fanout of a clock itself is limited, and one has to use some buffers to drive the reclockers. Reclocking obviously is required, as the clock quality put out by digital filters is lousy (jitter !), one reason to avoid them. Everyone is free to rely on the clock put out by digtal filters, I don't.
I know about groundbounce. If you have read my paper on supply decoupling, you'll see hands-on advices how to avoid most of it. In addition, I worked for Philips semiconductors on this subject, reducing on chip bounce by taking several measures in the field of layout, circuit design (flipflops, buffers) and on-chip decoupling strategies.
mr Ulas, I sense a lot of agression in the tone of your postings, could you explain your tone ?
Then finally, what would be your preferred clocking scheme ?
best
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