This may well be a crazy one, which serves only to demonstrate my ignorance of digital formats. But please be patient, particularly if I’m covering old ground – It maybe I dont have the vocabulary to search for the right thread.
So I’m trying to figure out my first DAC-from-scratch project. Unfortunately I’m 6000miles away from my soldering iron so this has to stay on the theoretical level.
I’m thinking of using (read want to) the TDA1541(a) with the DF1704 filter and there in lies the rub. Output from the DF1704 is quoted as ‘n’bit, MSB first, twos compliment, which I understand rules out using the simultaneous mode of the TDA1541(a)
But what happens if the data from the filter is supplied to the TDA1541(a) in I2S mode? I need two DAC chips I suppose, one for left one for right, but what, if anything, is going to come out of the iout pins?
If this IS just doomed to failure is there an alternative to the SAA7220 that can be set manually? (being able to source it would be a plus too)
Thanks in advance for any advice
Andy
So I’m trying to figure out my first DAC-from-scratch project. Unfortunately I’m 6000miles away from my soldering iron so this has to stay on the theoretical level.
I’m thinking of using (read want to) the TDA1541(a) with the DF1704 filter and there in lies the rub. Output from the DF1704 is quoted as ‘n’bit, MSB first, twos compliment, which I understand rules out using the simultaneous mode of the TDA1541(a)
But what happens if the data from the filter is supplied to the TDA1541(a) in I2S mode? I need two DAC chips I suppose, one for left one for right, but what, if anything, is going to come out of the iout pins?
If this IS just doomed to failure is there an alternative to the SAA7220 that can be set manually? (being able to source it would be a plus too)
Thanks in advance for any advice
Andy
I wondered when that'd come up.
thanks - I have a feeling I'll need all the luck I can get
I want to use the filter because I cant get past the theory of oversampling. vs Non-oversampling.
But I'll probably do both, I'm curious about the Non-OS sound, theoretically it should be a disaster - but I guess its really not.
Anyway the TDA1541 has 3 things going for it for this application
1 Theres LOTS of information about what it likes in terms of installation
2 Its regarded as a good Multibit dac (not Bitstream or Co-phase)
3 I have some.
thanks - I have a feeling I'll need all the luck I can get
I want to use the filter because I cant get past the theory of oversampling. vs Non-oversampling.
But I'll probably do both, I'm curious about the Non-OS sound, theoretically it should be a disaster - but I guess its really not.
Anyway the TDA1541 has 3 things going for it for this application
1 Theres LOTS of information about what it likes in terms of installation
2 Its regarded as a good Multibit dac (not Bitstream or Co-phase)
3 I have some.
Andrew, I'm also thinking of a design that sounds a little unorthodox, at least, as far as I can tell from these forums. Here it is:
CS8416 (standard S/PDIF receiver) ->
AD1896 (upsample 44.1 to 96) ->
PCM1704 or PCM1794 (bypassing internal DF) ->
I/V conversion
So, I want to use the AD1896 to upsample (and minimize jitter), and then convert to analog, but bypass the digital filtering on the DAC. To me, this seems like a hybrid between OS and non-OS. Whether it is the "best" way, I have no idea, but at least, it should be interesting to find out how it sounds.
CS8416 (standard S/PDIF receiver) ->
AD1896 (upsample 44.1 to 96) ->
PCM1704 or PCM1794 (bypassing internal DF) ->
I/V conversion
So, I want to use the AD1896 to upsample (and minimize jitter), and then convert to analog, but bypass the digital filtering on the DAC. To me, this seems like a hybrid between OS and non-OS. Whether it is the "best" way, I have no idea, but at least, it should be interesting to find out how it sounds.
andrew_whitham said:
The pair will work together in simultaneous mode, so long as you convert the two's complement data from the DF1704 into offset binary data.
I2S data into an I2S-capable device............
I need two DAC chips I suppose, one for left one for right, but what, if anything, is going to come out of the iout pins?
Why ? The I2S bus is a two channel serial bus and the TDA1541A is a 2 channel device.
DF1700/SM5813
PMD100
Thanks,
rfbrw, I'm a little overwhelmed by the conversion from i2s to offset binary, you appear to have to delay the data by one clock cycle. and to be brutal I dont think I kave the knowledge to do that
I expected you'd need 2 DAC chips because the DF1704 outputs bit clock, word clock and Data left / right. But In I2S mode the TDA1541A is accepting bit clock, word clock and Data.
Can you just connect the L/R data streams at the TDA1541A?
Andy
rfbrw, I'm a little overwhelmed by the conversion from i2s to offset binary, you appear to have to delay the data by one clock cycle. and to be brutal I dont think I kave the knowledge to do that
I expected you'd need 2 DAC chips because the DF1704 outputs bit clock, word clock and Data left / right. But In I2S mode the TDA1541A is accepting bit clock, word clock and Data.
Can you just connect the L/R data streams at the TDA1541A?
Andy
The I2S bus can carry 2's comp or offset binary data. Whether the data format is I2S, MSB justified, LSB justified, Sony, Sony/BB or packed is different from whether the number format of the data is 2s comp or offset binary.
The TDA1541A has three modes. I2S with 2's comp data, I2S with offset binary data and simultaneous with offset binary data. In the first two modes 2ch data is input serially and is demultiplexed in the dac, hence the need for only three input pins. In the third mode 2ch data is input simultaneously, requiring separate L and R input pins. The DF1704 will connect to the TDA1541A using the third mode but the data will have to be converted from 2's comp to offset binary. The DF1700/SM5813 and the PMD100 will also connect using the third mode but conversion is unnecessary as the choice of 2's comp or offset binary is pin selectable.
The TDA1541A has three modes. I2S with 2's comp data, I2S with offset binary data and simultaneous with offset binary data. In the first two modes 2ch data is input serially and is demultiplexed in the dac, hence the need for only three input pins. In the third mode 2ch data is input simultaneously, requiring separate L and R input pins. The DF1704 will connect to the TDA1541A using the third mode but the data will have to be converted from 2's comp to offset binary. The DF1700/SM5813 and the PMD100 will also connect using the third mode but conversion is unnecessary as the choice of 2's comp or offset binary is pin selectable.
Easily the most useful thing I learnt today
Thanks rfbrw,
That makes a bit more sense now. so I just spent an (another) hour or so staring at the datasheets and I see the problem - it just wont work!
(well not as you say without conversion)
Obviously there's a choice to be made, either I can accept more complexity in the transfer & conversion of data than I want to. Or I need to use different components, either the filter or the DAC.
I think I'll look for one of the PMD100 (or PMD200) chips, the datasheets for those seem to indicate that anything's possible. Hmm.... HDCD requires a 20 bit dac though
Incidentally I cant find a data sheet for the DF1700, even at BB. I take it that means its rare?
Oh well Back to the drawing board - its only electrons.
Thanks again its nice to get some expert guidance.
Andy
Thanks rfbrw,
That makes a bit more sense now. so I just spent an (another) hour or so staring at the datasheets and I see the problem - it just wont work!
(well not as you say without conversion)Obviously there's a choice to be made, either I can accept more complexity in the transfer & conversion of data than I want to. Or I need to use different components, either the filter or the DAC.
I think I'll look for one of the PMD100 (or PMD200) chips, the datasheets for those seem to indicate that anything's possible. Hmm.... HDCD requires a 20 bit dac though
Incidentally I cant find a data sheet for the DF1700, even at BB. I take it that means its rare?
Oh well Back to the drawing board - its only electrons.
Thanks again its nice to get some expert guidance.
Andy
The DF1700 is a re-badged SM5813, a device long discontinued.
www.datasheetarchive.com have both datasheets.
www.datasheetarchive.com have both datasheets.
Re: Easily the most useful thing I learnt today
Don’t give up. I think the DF1704/TDA1541 combo would be very interesting. All you have to do is delay the data ½ cycle, with respect to BCK, invert the MSB of each sample and generate the LE strobe at the falling edge of WCKO. It could be done with a few flipflops and xor gates.
andrew_whitham said:
Don’t give up. I think the DF1704/TDA1541 combo would be very interesting. All you have to do is delay the data ½ cycle, with respect to BCK, invert the MSB of each sample and generate the LE strobe at the falling edge of WCKO. It could be done with a few flipflops and xor gates.
oh is that all
Ulas,
It might be interesting but after all that manipulation of the data wouldnt you get a lot of jitter / other timing problems?
Plus I barely understand what you just wrote!
For me the phrase "descretion is the better part of valor" is definately applicable! As a first DAC project it seems unwise. I see scrap
Unfortunately I would like to know how it was done, even if I dont use that knowledge - its like alternative therapy...
Andy
Ulas,
It might be interesting but after all that manipulation of the data wouldnt you get a lot of jitter / other timing problems?
Plus I barely understand what you just wrote!
For me the phrase "descretion is the better part of valor" is definately applicable! As a first DAC project it seems unwise. I see scrap
Unfortunately I would like to know how it was done, even if I dont use that knowledge - its like alternative therapy...
Andy
Re: oh is that all
What is this obsession with jitter? There is only one place in the D/A conversion process where jitter matters and that is the moment the analog output changes to reflect the value of the next sample.
Do you have any idea how many gates and latches there are in a CS8414/DF1704/TDA1541 combo, not to mention what goes on in the CDP, and before that, all the gates and latches the signal goes through in the recording and mastering process. If all that seems to work OK, how can the addition of a few more gates and latches necessarily screw it up? If every clocked digital circuit were plagued with jitter, as you seem to think, computers wouldn’t work and we sure as hell wouldn’t be communicating via the Internet.
andrew_whitham said:
What is this obsession with jitter? There is only one place in the D/A conversion process where jitter matters and that is the moment the analog output changes to reflect the value of the next sample.
Do you have any idea how many gates and latches there are in a CS8414/DF1704/TDA1541 combo, not to mention what goes on in the CDP, and before that, all the gates and latches the signal goes through in the recording and mastering process. If all that seems to work OK, how can the addition of a few more gates and latches necessarily screw it up? If every clocked digital circuit were plagued with jitter, as you seem to think, computers wouldn’t work and we sure as hell wouldn’t be communicating via the Internet.
Re: Re: oh is that all
Admittedly, I've been banging my head against a brick wall about that. I'm avoiding it or anything that *might* cause the clock / data to get shuffled beacuse I dont yet fully understand its effects that's all... Sounds like I'm giving it more room than necessary.
But since there's be more mileage in this than I'd thought, I see why you delay the data a BCK half cycle (rising edge vs falling edge yes?) and I can see where the LE signal would be derived from, but why invert the MSB?
I have some reading to do...
or some plagiarisim to do
Ulas said:
Admittedly, I've been banging my head against a brick wall about that. I'm avoiding it or anything that *might* cause the clock / data to get shuffled beacuse I dont yet fully understand its effects that's all... Sounds like I'm giving it more room than necessary.
But since there's be more mileage in this than I'd thought, I see why you delay the data a BCK half cycle (rising edge vs falling edge yes?) and I can see where the LE signal would be derived from, but why invert the MSB?
I have some reading to do...
or some plagiarisim to do
blimey this is tricky.
I think we're at cross purposes
I was thinking the data has to go into the tda1541a using simultaneous mode (data left + data right). which is already offset binary.
I need therefore, to convert from "Binary twos compliment, MSB first, right justified audio data" to offset binary? And I think thats the timing charts below? (assuming I cut the right bits from the datasheets)
Actually the whole i2s aspect of this may have been an error. The i2s input on the TDA1541 is rated at 4x oversampling where the DF1704 only outputs at 8x.
Andy
I think we're at cross purposes
I was thinking the data has to go into the tda1541a using simultaneous mode (data left + data right). which is already offset binary.
I need therefore, to convert from "Binary twos compliment, MSB first, right justified audio data" to offset binary? And I think thats the timing charts below? (assuming I cut the right bits from the datasheets)
Actually the whole i2s aspect of this may have been an error. The i2s input on the TDA1541 is rated at 4x oversampling where the DF1704 only outputs at 8x.
Andy
Attachments
Sorry to intrude...
Andy, why don't you just connect I2S to your DAC chip and see if you like it???
(sorry rfbrw)
I'm always the first to recognize that I know nothing but I recently succeeded to make my first nonos DAC (yes, with the veteran 1543*4) from scratch, directly fed through I2S and I'm very happy with the result. Not the ultimate in detail but engaging and satisfactory.
Don't get mad at me, I'm only trying to help
Good luck
M
PS: what I2S capable transport are you using? I would love to find some cheap I2S transports
Andy, why don't you just connect I2S to your DAC chip and see if you like it???
(sorry rfbrw)
I'm always the first to recognize that I know nothing but I recently succeeded to make my first nonos DAC (yes, with the veteran 1543*4) from scratch, directly fed through I2S and I'm very happy with the result. Not the ultimate in detail but engaging and satisfactory.
Don't get mad at me, I'm only trying to help
Good luck
M
PS: what I2S capable transport are you using? I would love to find some cheap I2S transports
Maxlorenz
no I2S is actually available I was confusing Phillips 2's compliment with Burr-Browns, a fairly impressive demonstration of knowing nothing..
So aside form the thread's title I'm now just trying to figure out how you might link the two - filter to DAC - but my logic isnt that sharp.
Congrats on your dac, I dont know of any I2S 'transports' out there but, wouldnt any of the old philips players be i2s friendly. Anything shipping with a 1543 in it has to have i2s in there somewhere. right? And you can pick those up cheap!
(you'd also get a free oversampling filter)
Andy
no I2S is actually available I was confusing Phillips 2's compliment with Burr-Browns, a fairly impressive demonstration of knowing nothing..
So aside form the thread's title I'm now just trying to figure out how you might link the two - filter to DAC - but my logic isnt that sharp.
Congrats on your dac, I dont know of any I2S 'transports' out there but, wouldnt any of the old philips players be i2s friendly. Anything shipping with a 1543 in it has to have i2s in there somewhere. right? And you can pick those up cheap!
(you'd also get a free oversampling filter
)Andy
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