Re: Re: I2S Direct
Guido, Don't pull my leg.
Keep the Asynchronous Reclocker out of this discussion! It is NOT used in the I2S Direct scheme. If you don't have a schematic, pity for you. I do not advice using the ASR in the I2S Direct scheme but only with SPDIF after the CS8412. I do not want to place the Masterclock at the NON-OS DAC, period. And I do not want to generate (and divide) the clock at the DAC and feed it back to the transport, period.
The discussion is not about definitions. You only seed confusion!
I made a simple interface along the idea of Kal Rubinson and Audio Alchemy.
You missed why I use a buffer.
You missed why I don't use double terminated cables.
You missed that the three signals are together on one chip at the SAA7310 and the TDA1543.
You still missed that the Masterclock is not used at a NON-OS DAC and that only the Bitclock is used. For your information Masterclock in my Philips CD931 is 11.2896 MHz and Bitclock is about 2.8 MHz. You should know that, don't pull my leg about definitions
Do I make myself perfectly clear........?
Guido Tent said:
Guido, Don't pull my leg.
Keep the Asynchronous Reclocker out of this discussion! It is NOT used in the I2S Direct scheme. If you don't have a schematic, pity for you. I do not advice using the ASR in the I2S Direct scheme but only with SPDIF after the CS8412. I do not want to place the Masterclock at the NON-OS DAC, period. And I do not want to generate (and divide) the clock at the DAC and feed it back to the transport, period.
The discussion is not about definitions. You only seed confusion!
I made a simple interface along the idea of Kal Rubinson and Audio Alchemy.
You missed why I use a buffer.
You missed why I don't use double terminated cables.
You missed that the three signals are together on one chip at the SAA7310 and the TDA1543.
You still missed that the Masterclock is not used at a NON-OS DAC and that only the Bitclock is used. For your information Masterclock in my Philips CD931 is 11.2896 MHz and Bitclock is about 2.8 MHz. You should know that, don't pull my leg about definitions
Do I make myself perfectly clear........?
Re: Re: Re: I2S Direct
Hi Bricolo,
Yes you did understand me right. The TDA1543 has no masterclock input, only a digital filter has, or a Delta-Sigma DAC chip.
I did not gave a SAA7310 pinout for the Bitclock, WS and Data as it is more handy to connect the wires in the CD931 to the PCF2705P (I2S to SPDIF converter) at the components side. For the latter:
WS= pin 1
Bitclock= pin 2
DATA = pin 3.
Hope this helps.
Bricolo said:
Hi Bricolo,
Yes you did understand me right. The TDA1543 has no masterclock input, only a digital filter has, or a Delta-Sigma DAC chip.
I did not gave a SAA7310 pinout for the Bitclock, WS and Data as it is more handy to connect the wires in the CD931 to the PCF2705P (I2S to SPDIF converter) at the components side. For the latter:
WS= pin 1
Bitclock= pin 2
DATA = pin 3.
Hope this helps.
I2S Direct
Hi Andrea,
Glad the difference between Bitclock and Masterclock is now clear to you.
I omitted the 10 Ohm resistors as in Horowitz. These are for short circuit protection but I am using Lemo connector system that does not make a short while pulling out as RCA's do. Anyway I can't imagine you will use RCA's for this. Of course BNC can also be used. In Horowitz it is explained you have to use hefty logic buffers to drive coax cable. This can be done, even have some samples in the shoebox ready for it, but I wanted it to make as simple as possible.
Imagine when you have a short to ground or supply at the base of the transistors what will happen to the SAA7310. Then you have to learn how to desolder and solder a SAA7310 (44 pin SMD IC). So the buffer is there for precaution and the 2N4401's for cable driving.
Andypairo said:Well, I stay away for a couple of hours and things get hot!
The difference between IIS clock and master clock made me difficult to understand how to send the clock back to the transport, thank you Elso for pointing the question out, now is more clear.
To be true the EE is on vacation!
More seriously, I can analyze a circuit but I can't always tell from it what was the designer's purpose.
And yes, it is still on page 612 ( I have 2nd version too) but Horowitz uses a 10 Ohm from 5V to the collector of the BJT for circuit protection... don't know if I can leave the buffer out, have to take a look at the drive capability of the SAA7310, especially if I want to use some stacked TDA1543s.....
Cheers
Andrea
Hi Andrea,
Glad the difference between Bitclock and Masterclock is now clear to you.
I omitted the 10 Ohm resistors as in Horowitz. These are for short circuit protection but I am using Lemo connector system that does not make a short while pulling out as RCA's do. Anyway I can't imagine you will use RCA's for this. Of course BNC can also be used. In Horowitz it is explained you have to use hefty logic buffers to drive coax cable. This can be done, even have some samples in the shoebox ready for it, but I wanted it to make as simple as possible.
Imagine when you have a short to ground or supply at the base of the transistors what will happen to the SAA7310. Then you have to learn how to desolder and solder a SAA7310 (44 pin SMD IC). So the buffer is there for precaution and the 2N4401's for cable driving.
Re: Re: Re: I2S Direct
Elso,
Chill out mate.
Guido is absolutely right and is merely suggesting the ultimate
implementation of ANY DAC driven by I2S.
11.2896MHz XO best sit right next to DAC and reclock bitclock
edges with a DFF. The DAC OP current changes correspond to +
edge of bitclock so this is most important to reclock. The 11.2896
and 2.8224 are completely synchronous, there needs to be no
clock division at DAC. Clock merely needs to be buffered for
transmission back to transport.
I think Guido also reported improvements in reclocking WC and
data into DAC, I haven't tried this but I believe him
Now, big question WRT RF isolation, is it worth using VHQ
transformers on all lines? My feeling is yes, since the master
XO is next to DAC, there is (theoretically) no jitter penalty and
isolation should be a good thing. I will evaluate this soon.
Probably use some HBW Scientific Conversion trannies.
Cheers,
Terry
Elso Kwak said:
Guido, Don't pull my leg.
Keep the Asynchronous Reclocker out of this discussion! It is NOT used in the I2S Direct scheme. If you don't have a schematic, pity for you. I do not advice using the ASR in the I2S Direct scheme but only with SPDIF after the CS8412. I do not want to place the Masterclock at the NON-OS DAC, period. And I do not want to generate (and divide) the clock at the DAC and feed it back to the transport, period.
The discussion is not about definitions. You only seed confusion!
I made a simple interface along the idea of Kal Rubinson and Audio Alchemy.
You missed why I use a buffer.
You missed why I don't use double terminated cables.
You missed that the three signals are together on one chip at the SAA7310 and the TDA1543.
You still missed that the Masterclock is not used at a NON-OS DAC and that only the Bitclock is used. For your information Masterclock in my Philips CD931 is 11.2896 MHz and Bitclock is about 2.8 MHz. You should know that, don't pull my leg about definitions
Do I make myself perfectly clear........?
Elso,
Chill out mate.
Guido is absolutely right and is merely suggesting the ultimate
implementation of ANY DAC driven by I2S.
11.2896MHz XO best sit right next to DAC and reclock bitclock
edges with a DFF. The DAC OP current changes correspond to +
edge of bitclock so this is most important to reclock. The 11.2896
and 2.8224 are completely synchronous, there needs to be no
clock division at DAC. Clock merely needs to be buffered for
transmission back to transport.
I think Guido also reported improvements in reclocking WC and
data into DAC, I haven't tried this but I believe him
Now, big question WRT RF isolation, is it worth using VHQ
transformers on all lines? My feeling is yes, since the master
XO is next to DAC, there is (theoretically) no jitter penalty and
isolation should be a good thing. I will evaluate this soon.
Probably use some HBW Scientific Conversion trannies.
Cheers,
Terry
Re: Re: Re: Re: I2S Direct
I'm not sure if 11Mhz would be enough to reclock the IIS, even NON OS
Terry Demol said:
Elso,
Chill out mate.
Guido is absolutely right and is merely suggesting the ultimate
implementation of ANY DAC driven by I2S.
11.2896MHz XO best sit right next to DAC and reclock bitclock
edges with a DFF. The DAC OP current changes correspond to +
edge of bitclock so this is most important to reclock. The 11.2896
and 2.8224 are completely synchronous, there needs to be no
clock division at DAC. Clock merely needs to be buffered for
transmission back to transport.
I think Guido also reported improvements in reclocking WC and
data into DAC, I haven't tried this but I believe him
Now, big question WRT RF isolation, is it worth using VHQ
transformers on all lines? My feeling is yes, since the master
XO is next to DAC, there is (theoretically) no jitter penalty and
isolation should be a good thing. I will evaluate this soon.
Probably use some HBW Scientific Conversion trannies.
Cheers,
Terry
I'm not sure if 11Mhz would be enough to reclock the IIS, even NON OS
Re: Re: Re: Re: Re: I2S Direct
Hi Bricolo, Terry
Yes I agree reclocking with the masterclock from the player does not bring much in my experience. Been there done that. Yes I know I am <<un enfant terrible>> in this respect. Just my opinion and my experience. I think you will need a much higher frequency asynchronous clock like the one I was using.
With the I2S Direct scheme I did not hear much benefit from Asynchronous Reclocking. I will repeat the experiment with a 125MHz low jitter clock from Vite. The ASR was an idea to reduce the jitter originating in the SPDIF interface and the DIR's PLL.
I am not interested in a DAC with digital filter as I am on the NON-OS wagon since more than two years. So any schemes with digital filters and the Masterclock I leave to others.
Bricolo said:
I'm not sure if 11Mhz would be enough to reclock the IIS, even NON OS
Hi Bricolo, Terry
Yes I agree reclocking with the masterclock from the player does not bring much in my experience. Been there done that. Yes I know I am <<un enfant terrible>> in this respect. Just my opinion and my experience. I think you will need a much higher frequency asynchronous clock like the one I was using.
With the I2S Direct scheme I did not hear much benefit from Asynchronous Reclocking. I will repeat the experiment with a 125MHz low jitter clock from Vite. The ASR was an idea to reduce the jitter originating in the SPDIF interface and the DIR's PLL.
I am not interested in a DAC with digital filter as I am on the NON-OS wagon since more than two years. So any schemes with digital filters and the Masterclock I leave to others.
Re: I2S Direct
Hello Elso,
not being a DAC expert some things are still unclear, only a few months ago I didn't even imagine that I could build a DAC in a decent manner, now I know it can be done quite easily
I don't want to mess around with SMD chips, so I think I'll use the buffer (but maybe not the HC125, more likely to be a 244 or a 126)... but in case of "internal" placement of the DAC I'd probably omit the BJTs and the cable termination, leaving the buffer in to avoid problems wheen using multiple DACs.
Why do you think AC logic is like "black pest" .. i'm curious
Cheers
Andrea
Elso Kwak said:
Hi Andrea,
Glad the difference between Bitclock and Masterclock is now clear to you.
....
So the buffer is there for precaution and the 2N4401's for cable driving.
Hello Elso,
not being a DAC expert some things are still unclear, only a few months ago I didn't even imagine that I could build a DAC in a decent manner, now I know it can be done quite easily
I don't want to mess around with SMD chips, so I think I'll use the buffer (but maybe not the HC125, more likely to be a 244 or a 126)... but in case of "internal" placement of the DAC I'd probably omit the BJTs and the cable termination, leaving the buffer in to avoid problems wheen using multiple DACs.
Why do you think AC logic is like "black pest"
.. i'm curiousCheers
Andrea
Re: Re: I2S Direct
See for example :
http://www.diyaudio.com/forums/showthread.php?postid=81711#post81711
Cheers,
Hi Andrea,Andypairo said:
Hello Elso,
Why do you think AC logic is like "black pest"
Cheers
Andrea
See for example :
http://www.diyaudio.com/forums/showthread.php?postid=81711#post81711
Cheers,
Hi, Elso
Thank you fo the excellent explanation. Just wondering, if we want to put 4 or 8 1543s in parallel, will this buffer thing still work well? Probably not, right? Probably I will have to add in a reclocking circuit right before the DACs or simply give up this direct I2S scheme?
-finney
Thank you fo the excellent explanation. Just wondering, if we want to put 4 or 8 1543s in parallel, will this buffer thing still work well? Probably not, right? Probably I will have to add in a reclocking circuit right before the DACs or simply give up this direct I2S scheme?
-finney
Re: 4 or 8 TDA1543's parallel
Yes, Elso, but here we are driving a 1m line here. Hard to say. Another issue is the jitter, clock skew, etc. not easy things to meaure. As you have suggested, looks like experimenting is the only way to go.
Elso Kwak said:
Hi finney,
I would guess that the TTL load of 4 or 8 inputs is minimal // to the 50 Ohm. But you could observe your scope and see what happens.
Yes, Elso, but here we are driving a 1m line here. Hard to say. Another issue is the jitter, clock skew, etc. not easy things to meaure. As you have suggested, looks like experimenting is the only way to go.
I don't advice to use coax cable for transmit digital data if phase noise value of received signal is important. In this case differential transmitters/receivers and twisted pair provide lower phase noise than the coax. I usually use LVDS, PECL or RS485 transmitters/receivers, which has very low jitter (about 2ps) and more tolerants to power supply or coupling noises than emitter followers.
Re: Re: Re: Re: Re: Re: Re: I2S Direct
OK I understand now.
We seem to have gotten somewhat off course. The post
by Guido Tent was addressing *Synchronous* reclocking
of the DAC with master clock located next to DAC and sending
this clock back to transport. The XO was to reclock bitclock
of I2S into DAC. This is the absolute best way to implement
transport / DAC interface.
WRT 11.2896MHz frequency it is actually close to optimum
as XO's phase noise degrades above 10MHz. For example
comparing a typical very low phase noise XO of frequencies
10MHz and 100MHz, the 100MHz will have about 20dB worse
phase noise.
WRT LVDS, PECL or RS485, the whole idea of having master
clock in dac is to preclude jitter induced by interface.
I would think then the most important factor would be RF
isolation.
WRT emitter follower tolerance to PS noise depends how it's
implemented. With just +5 available and unbalanced yes,
however I remember a scheme proposed by Wildmonkeysect
(I thinks thats his name) which had fully bal EF's feeding a
transformer which looked pretty good for coax.
Cheers,
Terry
Bricolo said:
I'm not sure you understand asynchronous reclocking
OK I understand now.
We seem to have gotten somewhat off course. The post
by Guido Tent was addressing *Synchronous* reclocking
of the DAC with master clock located next to DAC and sending
this clock back to transport. The XO was to reclock bitclock
of I2S into DAC. This is the absolute best way to implement
transport / DAC interface.
WRT 11.2896MHz frequency it is actually close to optimum
as XO's phase noise degrades above 10MHz. For example
comparing a typical very low phase noise XO of frequencies
10MHz and 100MHz, the 100MHz will have about 20dB worse
phase noise.
Kochkurov Maxim said:
WRT LVDS, PECL or RS485, the whole idea of having master
clock in dac is to preclude jitter induced by interface.
I would think then the most important factor would be RF
isolation.
WRT emitter follower tolerance to PS noise depends how it's
implemented. With just +5 available and unbalanced yes,
however I remember a scheme proposed by Wildmonkeysect
(I thinks thats his name) which had fully bal EF's feeding a
transformer which looked pretty good for coax.
Cheers,
Terry
I2S Drivers
Hi Andrea,
Why not,do you consider for driver the I2S
system these Chips:
MC10H352 this is a traslator CMOS to PELC for driver, and the MC10H350 this is
a traslator PELC to CMOS for receiver.
The lines are in balacing system it is better
for noise,jitter and etc..
Typical Propagation Delay:1.5nS
Typical Rise time/Fall time:0.3nS
The only problem is that these chips are a
little expensive.
Jesus
Hi Andrea,
Why not,do you consider for driver the I2S
system these Chips:
MC10H352 this is a traslator CMOS to PELC for driver, and the MC10H350 this is
a traslator PELC to CMOS for receiver.
The lines are in balacing system it is better
for noise,jitter and etc..
Typical Propagation Delay:1.5nS
Typical Rise time/Fall time:0.3nS
The only problem is that these chips are a
little expensive.
Jesus
Some words about typicaly jitter values of differential transmitters/receivers, logic gates and digital isolators.
ADM1485 5ps RMS
SN65LVDS050 2ps RMS
MC10124/125 0.8ps RMS
100PU124/125 0.2ps (???) RMS
74LS family 8ps RMS per gate
74HC family 6ps RMS per gate
74ACT family 3ps RMS per gate
74AC family 2ps RMS per gate
74ABT family 0.8ps RMS per gate
MC100 family 1.5 ps RMS per gate (russian equivalent is K1500)
MC10 family 0.6ps RMS per gate (russian equivalent is K500)
100 family 0.1ps(???) RMS per gate (russian military aerospace equivalent of MC10)
AD8611 1 ps RMS (I measure only 5 items, results maybe has statisticaly unreliable)
ISO150 4 ps RMS
ADUM1100BR 4 ps RMS
100PU124, 100PU125 (russian transcription is 100ÏÓ124, 100ÏÓ125) is russian miitary aerospace equivalent of MC10124/125. It cost <1USD www.chip-dip.ru
ADM1485 5ps RMS
SN65LVDS050 2ps RMS
MC10124/125 0.8ps RMS
100PU124/125 0.2ps (???) RMS
74LS family 8ps RMS per gate
74HC family 6ps RMS per gate
74ACT family 3ps RMS per gate
74AC family 2ps RMS per gate
74ABT family 0.8ps RMS per gate
MC100 family 1.5 ps RMS per gate (russian equivalent is K1500)
MC10 family 0.6ps RMS per gate (russian equivalent is K500)
100 family 0.1ps(???) RMS per gate (russian military aerospace equivalent of MC10)
AD8611 1 ps RMS (I measure only 5 items, results maybe has statisticaly unreliable)
ISO150 4 ps RMS
ADUM1100BR 4 ps RMS
100PU124, 100PU125 (russian transcription is 100ÏÓ124, 100ÏÓ125) is russian miitary aerospace equivalent of MC10124/125. It cost <1USD www.chip-dip.ru
Buffer choice
Hi Kochkurov maxim,
This is the first step for the designer topology.
I´m very interesting to buy the russian equivalents becouse in Spain the familiy
MC10 is about 8€..
But I´dont undestand your web page becouse it is in russian.
I´ll sent at you particular email for most information.
Jesus
Hi Kochkurov maxim,
This is the first step for the designer topology.
I´m very interesting to buy the russian equivalents becouse in Spain the familiy
MC10 is about 8€..
But I´dont undestand your web page becouse it is in russian.
I´ll sent at you particular email for most information.
Jesus
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