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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
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Old 19th June 2021, 12:13 PM   #3911
wlowes is offline wlowes  Canada
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Great description. BTW, it gets even better with time. The more focus needed items will become more obvious with time under power.
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Old 19th June 2021, 02:47 PM   #3912
andrea_mori is offline andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Default Note on the TWTMC-DRIXO 5/6 MHz semi-finished boards

5.6448 MHz and 6.144 MHz crystals have very high Q (more than 2M) and high ESR.
We have seen with some crystals that the oscillator needs long time to start and sometimes it doesn't even start.
In this case you can replace R24 (1K) with 1.2K, 1.5K or 1.8K resistor so it will start faster.
The increased value of R24 does not affect the phase noise performance.
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Old 19th June 2021, 07:13 PM   #3913
clsidxxl is offline clsidxxl  France
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Quote:
Originally Posted by wlowes View Post
Great description. BTW, it gets even better with time. The more focus needed items will become more obvious with time under power.

wlowes,After what duration under power the sound seemed to you stabilize,
with the DRIXO which is impressive it's the feeling of having a higher level of volume,as said Supersurfer no need to mount the potentiometer like before,it's much more dynamic.
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Old 19th June 2021, 08:03 PM   #3914
wlowes is offline wlowes  Canada
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clsidxxl.. It is hard to say how long to settle in. I think after 2 weeks it had become stable. It is powered now for almost 2 months. Listening just yesterday it struck me that it seemed the best ever. Normally you make a change, acclimatize and the impact fades. This continues to impress and IMHO the pleasurable aspects continue to improve.
In that time however, I added ReclockPi which had an impact, and then gave ReclockPi a dedicated power supply. This also had an impact. I tend to use capacitors that are notoriously slow to settle, so it's hard to know how much is the evolution due to Drisco settling or these ancillary bits.
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Old 19th June 2021, 09:18 PM   #3915
clsidxxl is offline clsidxxl  France
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Thanks wlowes,I look forward the FIFO Lite,the DRIXO will be fully exploited.
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Old 19th June 2021, 10:22 PM   #3916
diyiggy is offline diyiggy
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Fifo lite ?


what are your power Drixo set-up both of you ? Cells ? Regs always switched on from the mains ?


Are there decoupling differences in both of your clock layout ?


Devils are in the details. I.e. and for what it worths, as you are not at iso layouts, I have always suspicion about what one claims as the main enhancement factor.


I have no real doubt about the circa 3 days minima powering on of the crystal -is there a difference if it is cells, super caps, always powered on good regs ?-


Wolwes is making a hard tweak with caps (I'm glad he is using acrylic caps) of all sort (iirc Black Gate that works fine around digital stuffs).


What I mean is the set up are maybe different enough to be prudent about what is causing the enhancement (supercaps as a wall grid electricity stabiliser ?!... that makes the country more equal with the electricity quality provided ?)


That's crazy, as always, as few things can change sota designs with simple things : decoupling, power supplies,etc . I believe it's not always easy to highlight as we have all different layout, and not the less important : the electricity quality that comes out of the walls...
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Last edited by diyiggy; 19th June 2021 at 10:34 PM.
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Old 19th June 2021, 11:17 PM   #3917
wlowes is offline wlowes  Canada
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I believe FIFO lite is Andrea's FIFO v1.0 as opposed to 2.0 which will be his no cost barred SOTA attempt. As I understand it, his value proposition for FIFO lite is jitter on all I2S lines close to clock jitter, and separation of Rpi / FIFO to isolate noise. Ian countered with StationPi for isolation in compact form factor and then ReclockPi to preserve clock fidelity across all signals. I can vouch for ReclockPi delivering on it's claim. I soon will put in StationPi and will then report on that. I've reported on my approach to power so I'll leave that to clsidxxl.
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Old 19th June 2021, 11:49 PM   #3918
andrea_mori is offline andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
The FIFO Lite is here
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

The hardware is ready, but we are still working on the software because it's very complex due to the versatility of the board.

As soon as the software will be ready we need the help of some members who would like to test the first batch of the board with their current DAC.
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Old 20th June 2021, 01:30 PM   #3919
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Ah, ok, thanks. I haven't checked it yet. Some readings to come, so.
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Old 20th June 2021, 05:31 PM   #3920
clsidxxl is offline clsidxxl  France
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diyiggy, i have the PSU UGL always on since 1 week,Andrea has demonstrated
with measures that there are no big differences between(a good) PSU and Lifpo4 batteries.
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