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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
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Old 17th October 2020, 09:53 PM   #2921
Alexiss is offline Alexiss  Sweden
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Quote:
Originally Posted by MarcelvdG
Thanks, but how does measuring how well the jitter of an AES3 or S/PDIF interface is suppressed help in assessing the effect of the quality of a master clock?

Edit: I see that my question was answered in the thread that post 2919 links to: it doesn't.
Hi Marcel.
Nobody claimed it did
I wrote:
"I still find it to be a useful indicator of general problems in separate Transports/dac set-ups."

That is: in separate Transport/DAC setups, which inadvertently use the SPDIF protocol, being the case for most "semi-synchronous" (MCK inside Transport, dac PLL-locked to Transport) front-end set-ups out there.
Most certainly in the case of the now ancient Forsell Air Reference front-end.

This was aimed at those people who still use such set-up where the Master is not located on the DAC side.

Cheers

Last edited by Alexiss; 17th October 2020 at 10:08 PM.
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Old 17th October 2020, 10:32 PM   #2922
MarcelvdG is offline MarcelvdG  Netherlands
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Thanks, that clarifies it.
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Old 18th October 2020, 11:05 AM   #2923
andrea_mori is online now andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Default TWTMC-DBM Frequency doubler

I attach a picture of the new frequency doubler and a pair of phase noise plots (5 to 22 MHz and 11 to 22 MHz).

Adding a pair of doublers to the 11.2896 MHz oscillators you can expect around -127 dBc at 10 Hz from the carrier for a 45.1584 MHz oscillator, that's an exceptional result at such this frequency.
Attached Images
File Type: jpg TWTMC-DBM_01.JPG (227.0 KB, 464 views)
File Type: png TWTMC-DBM 56448 to 225792 - Batt att6dB.png (135.2 KB, 458 views)
File Type: png TWTMC-DBM 112896 to 225792 - Batt att6dB.png (134.1 KB, 448 views)
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Old 18th October 2020, 11:13 AM   #2924
andrea_mori is online now andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Default TWTMC-STS Sine to square converters

I attach a picture of the Sine to square converter (SX and DX to fit Ian's FIFO) and a pair of phase noise plots (22.5792 MHz and 5.6448 MHz).

The close in phase noise at the output of the squarer is the same of the base sine wave oscillators, only a little higher noise floor due to the noise added by the gates.
Attached Images
File Type: jpg TWTMC-STS_04.JPG (131.3 KB, 450 views)
File Type: png Driscoll xo22579 vs Squarer w- Battery 3V3 att6dB.png (152.9 KB, 412 views)
File Type: png Driscoll xo56448 vs Squarer w- Battery att6dB.png (157.7 KB, 142 views)
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Old 18th October 2020, 11:29 AM   #2925
TNT is offline TNT  Sweden
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
45Mhz, @10 Hz, -127 dBc...

8-o insane.

//
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Old 18th October 2020, 01:48 PM   #2926
dddac is offline dddac  Germany
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
TNT,
45Mhz, @10 Hz, -127 dBc...
8-o insane.


What you refer to still need to get squared?

If I look at the square 22MHz graph this is -125dBc
So if you want 45 out of that, according to Andrea after doubling you lose another 6dB?

so you end up for the 45Mhz in square wave at -119dB? is that correct?
is my line of reasoning correct Andrea? Please correct me if this is not the case.
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Old 18th October 2020, 02:11 PM   #2927
andrea_mori is online now andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Your reasoning is wrong, the sine to square converter does not increase the close in phase noise, as you can see in the plot the sine wave output 22 MHz oscillator has -125.1 dBc at 10 Hz from the carrier, while after the squarer is -124.9 dBc, so exactly the same.

You are wrong because you are looking at the base 22MHz oscillator, but if you look at the phase noise plot of the base 11MHz oscillator followed by one frequency doubler (so 22 MHz at the output) you can see -133dBc at 1 Hz from the carrier.
Then add the theoretically 6dB for one more frequency doubler and you finally get exactly -127dBc at 10 Hz from the carrier with 45.1584MHz output.

The sine to square converter only increase the noise floor but not the close in phase noise of the sine wave oscillator.
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Old 18th October 2020, 02:18 PM   #2928
dddac is offline dddac  Germany
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
thanks Andrea for the clarification
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Old 19th October 2020, 12:04 AM   #2929
mars2 is offline mars2  Switzerland
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Congratulations Andrea, the results look very promising, especially the square converter for 22MHz!

Quote:
Joking aside I don't really like the sound of the delta-sigma DACs,...
The Sabre is not a delta-sigma DAC. According to White Papers, they use their own proprietary HyperStream modulator, which is very linear and noise free (>160dB!), together with further benefits.


Quote:
Originally Posted by Alexiss
SABRE dac chips are not DA converter chips, they are converter systems, containing a lot of additional circuitry (SRC, MUX, DMUX, various DF's, Reclockers, switches aso).
By the time the clock signal reaches the converters, it's been heavily polluted.
The Sabre chips are built up of several internal (software configurable) blocks which allow them a great flexibility. Insofar, you can call them "converter systems".

The following points will clarify some advantages of this flexibility:

a) You can run them in synchronous master mode, using the I2S input (for my taste clearly better than SPDIF, without a MUX) and a standalone ultralow jitter masterclock oscillator.
...and the clock signal will be as pure as it can get.
b) It`s possible to supply up to eight parts of the chip completely independent. Every part over its own, specifically designed supply. For example ultra low noise L/R-analog supplies, digital core supplies with fast correction amplifiers etc.

Furthermore, your absolutely free, to add for example an outsourced interpolation filter, if you`re not pleased with the internal one.

These, amongst others, are the reasons, why professional and high-end gear manufacturers opt for the Sabre.

Given a (top) front-end DAC, along with an ultralow noise clock, I made the following experience:
Despite beeing a TDA1541, PCM63, AK4399 or ES9038PRO implementation, it`s the output stage, resp. I/V-converter, together with the following preamplifier/buffer, that has great impact on the resulting sound and can make a huge difference.

Last year, I had the chance to compare a TDA1541 top of the notch implementation against my highly developed Sabre.
Both played on an extraordinary high level, the differencies have been marginally and their sound was as musical as it can get
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Old 19th October 2020, 06:59 AM   #2930
janho12345 is offline janho12345  Germany
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Quote:
Originally Posted by andrea_mori View Post
I attach a picture of the new frequency doubler and a pair of phase noise plots (5 to 22 MHz and 11 to 22 MHz).

Adding a pair of doublers to the 11.2896 MHz oscillators you can expect around -127 dBc at 10 Hz from the carrier for a 45.1584 MHz oscillator, that's an exceptional result at such this frequency.
Hi Andrea,

Might I ask (only for educational purpose) what the frequency mixer on “TWTMC DBM” is for?
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