ESS9018 - try new, try more...

[Coris]

I think to start this new thread based on my own recent experience with this ultimate DAC.

I intended in the last time to change the ESS9018 clock oscillator, but I had not at that moment a right one. So I used an 106 Mhz for that max clock frequency specified in datasheet (100 Mhz).
It was accepted very well by ESS9018...
So, afterwords I`ve tried more. I bought one of 125Mhz and one 150Mhz. It was OK with 125Mhz, but didn`t work with 150 Mhz. So, my conclusion was that the limit have to be in this range (125 - 150 Mhz).
Recently I`ve tried with an 133,3 Mhz. It worked!
I have to say that the result of those experiments have been appreciate only perceptual, without very close measurements or any deeper analyses of what is possible to happen inside the chip at this high clock frequency. I had not that time to get closer/deeper in to this. I used both FLAC files and SACD/DSD. Even on ordinary CDs (44,1 khz sampling), the sound is fantastic The resulting sound after this upgrade is just exceptional in details. I never heard a such deeper and sophisticated bass, and the sound stage is amazing, comparing with an 100Mhz clock.
I can not say that ESS9018 it sounds not well with an 100Mhz clock. It could be stupid to state like this. But is a perceptual positive result after changing to a higher clock frequency. The details increasing in the sound is easy to notice.

By the way, my experiment object/DAC is not an very impressive one as design... I had not yet a Buffalo 3 PCB design at the experiment moment... But anyway this one it`s work very well after the modifications one can see in the picture. I think to take a look more seriously on this subject based on a Buffalo mounted ESS9018.

The point is now to share this experience, and invite you to come with your comments, impressions and even a closer look in to this field.

[regiregi22]

Amazing experiments, it would be interesting to heard TP about the results of their experiments.

[marce]

100MHz clocks, I'd be interested in some scope shots of the clock at the device pin.

[Russ White]

Originally Posted by regiregi22

Amazing experiments, it would be interesting to heard TP about the results of their experiments.

We consulted quite a lot with ESS on the subject.

The ES9018 actually begins to lose dynamic range (very measurable) as the clock speeds go past the rise and fall times specified in the datasheet. I was not the first to say this, Dustin Forman the chip designer was. While consulting with him we found that the DAC begins to measure worse after 100Mhz and that the best range is between 40-100Mhz and ~80Mhz is actually the sweetest spot when we measured our DAC by a very slim margin. 100Mhz still sounds and measures quite well but is more forgiving when the DPLL needs to lock onto sample rates > 352khz.

I have tried all sorts of clock frequencies using excellent clocks and personally found anything > 100Mhz less desirable than either 80Mhz or 100Mhz.

Still this poster is not using a Buffalo DAC so I cannot really say much about his experiments, except good luck, and have fun.

Cheers!
Russ

[Coris]

Originally Posted by Russ White

We consulted quite a lot with ESS on the subject.

The ES9018 actually begins to lose dynamic range (very measurable) as the clock speeds go past the rise and fall times specified in the datasheet. I was not the first to say this, Dustin Forman the chip designer was. While consulting with him we found that the DAC begins to measure worse after 100Mhz and that the best range is between 40-100Mhz and ~80Mhz is actually the sweetest spot when we measured our DAC by a very slim margin. 100Mhz still sounds and measures quite well but is more forgiving when the DPLL needs to lock onto sample rates > 352khz.

I have tried all sorts of clock frequencies using excellent clocks and personally found anything > 100Mhz less desirable than either 80Mhz or 100Mhz.

Still this poster is not using a Buffalo DAC so I cannot really say much about his experiments, except good luck, and have fun.

Cheers!
Russ

I understand well what about datasheet reveal in this case. It still only a question here: why one can perceptual notice an improvement using these higher clock frequencies?

I`m still waiting for somebody else trying the same on different DAC platforms and come with own impressions... That is actually the reason of this thread.

[Russ White]

Originally Posted by Coris

I understand well what about datasheet reveal in this case. It still only a question here: why one can perceptual notice an improvement using these higher clock frequencies?

Very simply the mostly likely reason is because one *wants to* hear the difference, There is nothing wrong with that.

[Coris]

Originally Posted by Russ White

Very simply the mostly likely reason is because one *wants to* hear the difference, There is nothing wrong with that.

I think is not that simple as you want to be... But anyway, everybody with his placebo...

I will stop here to answer to you, because the meaning with this thread is something else...

[barrows]

As an aside, but on the same topic, have you tried synchronous clocking? This is going to be my next experiment with the Buffalo II. I have an async USB interface which can provide the masterclock. My plan is to upgrade the oscillators on the USB interface to Crystek CCHD-957s when they become available, and at that point, try synchronous clocking the ESS 9018 from the MC feed over I2S. I am just curious to see what the DAC will sound like without the ASRC, and "virtually" disabling the DPLL.
In my past experience, I have preferred other DACs (TI 1798, Wolfson 8741) without any ASRC, provided that the data feed is low jitter to start with.

[Russ White]

Originally Posted by barrows

As an aside, but on the same topic, have you tried synchronous clocking? This is going to be my next experiment with the Buffalo II. I have an async USB interface which can provide the masterclock. My plan is to upgrade the oscillators on the USB interface to Crystek CCHD-957s when they become available, and at that point, try synchronous clocking the ESS 9018 from the MC feed over I2S. I am just curious to see what the DAC will sound like without the ASRC, and "virtually" disabling the DPLL.
In my past experience, I have preferred other DACs (TI 1798, Wolfson 8741) without any ASRC, provided that the data feed is low jitter to start with.

I certainly have. It works quite well and sounds exceptional, but you have to be extremely careful how you get the master clock from here to there.

I have a really cool method of doing that which I will share soon.

It doesn't just virtually shut down the DPLL, it very actually stops doing anything.

[barrows]

I look forward to hearing about your clock distribution method. Very cool that you are working with synchronous clocking. From what I have heard from engineers I respect on clock distribution, it appears it is very hard to keep low phase noise when transmitting a clock signal...
Yeah, on the DPLL, that is why I put "virtually" in quotes-my understanding is that the DPLL would still be active but would not be actually doing anything as the clocks are now synchronous, and woudl not need to be synched.