Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

Hello,

I searched the forum and didn’t find an answer to this question (apologies if I missed it).

My current setup is simple:
RPI 4b + ProtoDAC (TDA1387 x8)
(Running moOde + Roon bridge)
(Power: iFi Power 5V -> RPI -> ProtoDAC via GPIO)

I plan to improve it with:
1-Cleaner power (several options), and
2-FifoPi Q7 reclocker.

Inserting the Q7 between RPI and ProtoDAC requires an adapter with GPIO pins 2-4 removed in order to provide 5V to the DAC, as mentioned earlier on this forum.

So I need 3 clean power sources:
1- 5V to RPI
2- 5V to ProtoDAC
3- 3.3V to Q7

If money (and space) was no object, I could use 3 UcPure packs.

If not, perhaps one UcPure MkIII 5V w parallel DC cables to the RPI and DAC, and one UcPure MkIII 3.3V for the Q7. (Any comments on using parallel - or Y cables?)

If not, then I’m wondering: Where is it the most critical to have clean (no ripple) and highly available (low ESR, high Amperage) power? My guess would be at the DAC, because when the sound signal changes abruptly, the OpAmp needs to be able to feed the I/V stage without being limited by a PS that cannot cope with the sudden current demand.

On the other hand, the RPI’s job is to feed the bit stream to the I2S interface, which is not particularly demanding in terms of Amps, but could still benefit from a really quiet DC source.

If my reasoning is right, I could use my iFi Power 5V on the RPI, and use UcPure packs for the DAC and Q7.

I thank you in advance for your comments!