I said that you can not recover the sampled signal in analogue again because the ideal LP filtering (ask Nyquist about it) is only theory because you would need all the samples for that starting from a signal appears in time. You can only approximate that with various LP filters, like ZOH, or LC for the PWM. So if you sample any signal which is derived from this non-ideal LP filtered signal, the residual spectral components from the periodic discrete-time domain spectra, around the integer multiples of Fs, will be transposed to the baseband (as you know this). This can be canceled but not on the way you mentioned.
Why? The resolution of the ADC determines the noise floor of digitized signal. The lower the frequency to be sampled the higher resolution ADC is needed because otherwise the noise will be correlated with the sampled signal.
Resampling is a chewed off bone, everybody does that who can't make nonlinear error correction of equidistant time sampled signal fed PWM. You can only cancel the distortion of the equidistant sampled signal fed PWM in the baseband with that, and then that will be the approximation of analogue PWM (as you know). You will still have the carrier harmonics and their sidebands which will be overlapped to the baseband during sampling the LPF-ed output and that will cause larger distortion than the non-resampled PWM could cause by itself.
There is something else what you don't want to reveal. Abusement of unskilled people is not a fair behavior just only for a hype, or advertisement. As I wrote I know those parameters can be reached and know how can those be reached as well, and I'm sure that the Zetex chip can do that, but this is a technical forum and I think doing technical abusement and discrediting skilled people only for a hype or aggressive advertisement is not a fair thing even not for disguising an innovation.
P.S.: If I were you I wouldn't apply high-end DAC (and I haven't paid for that for you 😀) if the input signal is already known. The substraction can be made with high precision digital operations and there wouldn't be a slow (maybe the highest delay) component which the control-loop should be aligned to. And I think there's no need to say that making a feedback doesn't do the output equal to the reference signal. It can only reduce the error between them by the open-loop gain of the control-loop at the given frequency (as you know). The other thing is there is no need for such a high carrier frequency PWM. We obtained that quality level with half of that.
And if you can't prove your statements you should at least confess that those were not true.
Gyula said:
Since you don't seem to know how either sampling theory, the electronics industry or a feedforward/feedback circuit like the DDFA works here are a few key points:
1. You don't need an ideal LPF to recover the analogue output signal from a PWM or sigma-delta DAC unless you're going to resample it or your hearing extends up to 1MHz -- in fact if the speakers don't care about a high signal at these frequencies you don't need any filtering (except to meet EMC requirements).
2. If no intermodulation products appear within the audio range then you can't hear them, it doesn't matter what happens at hundreds of kHz, and these products don't magically get transposed to the baseband -- errors out-of-band have no effect inband. A PWM DAC is no different to a sigma-delta DAC in this respect, both generate large signals above the audio band before filtering.
3. A system using an "ideal" reference DAC and digitising just the error signal using an ADC is well known in other fields (like telecomms) and means the performance required of the feedback ADC is greatly reduced; the performance is then limited by the reference DAC not the error feedback ADC, assuming that the ADC can correctly digitise the average error over a pulse including the edges.
4. Adaptive error modelling and feedforward to cancel distortion is likewise well known in such fields, and also reduces the performance required for a wideband feedback control loop (which the DDFA has anyway, as I explained already).
5. The high PWM frequency is needed to get enough noise shaping to push the inband noise well below -120dB, in exactly the same way that sigma-delta DACs need to be highly oversampled.
6. I can't disclose any details about the Zetex DDFA that haven't already been made public due to confidentiality agreements. I'm not trying to hype their system here, just pointing out that the end result is a PWM amplifier with performance like a high-end DAC. I've seen the measurements (and these have been published) and they're difficult to argue with.
IVX said:
Not if the input signal is digital, and you want to combine the DAC function with DSP for equalisation, limiting, crossover, volume control...
(which is where this thread started)
phase_accurate said:
Obviously there are limits to how bad a supply you can use; what I meant is that the cost saving is significant compared to other digital-input class-D amplifiers which are much more reliant on a high-quality power supply, not having >80dB PSRR.
OK good point ! So how much voltage drop (or overvoltage as well) can it handle ?
Regards
Charles
IVX said:
This is based on the D2Audio DAE2
http://www.intersil.com/audio/DAE2/DAE-2 Product Sheet.pdf
which appears to offer similar functionality to the Zetex chipset, except for being 4 channels instead of 8 -- but the devil is in the details, I wouldn't like to speculate how the performance of the two compares since I only have knowledge of the Zetex one.
The THD+N doesn't look as good, but whether this can be heard or not is a matter for endless argument -- however since a lot of the audio market is (unfortunately?) spec-driven...
phase_accurate said:
You'll have to ask Zetex 🙂
(but AFAIK "unregulated" here means exactly that, so I expect the answer will be "quite a lot")
If you will be able to describe sampled signals in the frequency domain, find the concept of "undersampling" or "synchronous sampling" which obtain the downmixing of carrier-based signals to the baseband by the sampling itself. So if you sample the "doesn't matter" signals those will be put to the audible range. So it's not a magical thing as you thought, it's only the concept of "undersampling". Check this if you don't know with more than twenty years of experience (in Chip Design) : http://en.wikipedia.org/wiki/Undersampling . It's a usual method to get the signal from higher frequencies above Fs to around 0 Hz. Something magic for you, something obvious for others.
Lie. A Sigma-Delta DAC can operate much higher switching frequency than a PWM DAC can. Those magnitudes higher frequency components can be suppressed by an analog filter easily. But the case is different for PWM because that has fixed switching frequency which is much lower than a Sigma-Delta's carrier and the output LPF can't suppress that. The residual of these higher frequencies is the visible swing on the output after the LPF, which is undersampled by the feedback ADC sampling the error signal derived from that output. And this will happen: http://en.wikipedia.org/wiki/Undersampling
Learn the basics of signal processing. And in the meantime do businesslike advertisements of ZXCD chipset with lies and discrediting skilled people in order to sell them. Take it easy, take it obvious, it's the fact.
Gyula said:
I suggest you read Zetex's patent and their AES papers. Go to here
http://ep.espacenet.com/advancedSearch
and enter "digital amplifier" as title keywords and "zetex" as applicant.
Then build an *accurate* mixed discrete/continuous-time model of the system to mimic the analogue output/reference/feedback paths (but you might need simulation tools costing >100k dollars to do this, not to mention weeks of CPU time on a similarly-priced multiprocessor compute grid array ;-) and you'll find there is *no* aliasing of out-of-band intermodulation components into the audible band.
There's no undersampling which can cause aliasing (unlike many of the systems I've designed), the error signal is integrated and then A/D converted at an effective sampling rate >100Ms/s (the same as the pulse width resolution of the DAC) -- if you don't believe this then that's your problem, I'm not going to tell you how it's done so you'll have to work out for yourself ways that this is feasible.
The fact that that the PWM frequency (850kHz) is somewhat lower than a typical sigma-delta DAC (>2MHz) is irrelevant so long as the system is correctly designed so that aliasing doesn't happen.
Before accusing somebody of lying you should check your facts; everything I've said can be backed up by simulation, measurement, and correct interpretation of how such a PWM DAC with a reference path and error ADC works -- not Wikipedia.
Maybe it's also not a good idea to pick a technical fight with someone who has about 50 patents in this subject area, especially not by telling them that they don't understand the basics of signal processing, ADC and DAC design.
Unless you come up with more sensible and technically correct arguments I'm not going to bother continuing this discussion.
Since someone asked earlier when this would make it into a product which they might be able to hack/play with, here's an answer I just picked up from a Google news alert -- but probably not the one hoped for...
http://www.twice.com/article/CA6659474.html
I guess nobody's going to spend $5000 on one and then pull it to pieces :-(
Ian
http://www.twice.com/article/CA6659474.html
I guess nobody's going to spend $5000 on one and then pull it to pieces :-(
Ian
Do you think I didn't run such kind of simulation e.g. yesterday? I usually run 2.2 million points simulation of our ~500k gate count design, what takes 1.5 hours on my notebook, to be able to do 2^21 points FFT of the output signal, and then I usually stare at the results of ~140 dB SFDR with no harmonic distortion (THD is absent in simulation, no harmonics above the noise floor in our design). We made this DDFA for ourself. I believe that you designed many mixed signal ASICs but if you consider your posts in this topic from the beginning you can see that advertising something and telling hoaxes to the forum dudes in order to sell some pieces of an 850 kHz PWM shi*, so I think it is not the best place for this action. It's a professional forum, some posters are graduated EEs. You can discuss its operation or announce some innovation or new product or anything, I don't care. But stating lies to be true against somebody and discredit him when he asks you for provement of your statements (what you have never tried to comply) and moreover doing this with Chip Design experience in order to sell some piece of that 805 kHz PWM ... is not a fair behavior.
Gyula said:
Read my last post. I'm not the one using the word "liar". Everything I've said can be and has been verified.
If you think that simply simulating lots of modulator clock cycles (on a notebook, in an hour or two) and doing an FFT will give you the right answer, then you really don't understand the problem -- after all, you were the one who correctly pointed out that this is an analogue system, not a digital one 🙂
To get an accurate prediction of this level of performance you need to do a high-accuracy (microvolt resolution with around 1ps timestep) mixed-signal (analogue+digital) simulation of the closed loop, including package and chip parasitics (inductance and capacitance, and pin-to-pin coupling) as well as the complete analogue circuit and the digital modulator.
Like I said, this really isn't a simple design problem that amateurs can deal with -- I have access to the best design and simulation tools available and it was still a very difficult task to simulate (more than 1 week of CPU time per run on a multiprocessor system with 64G of RAM).
If you still don't understand how a feedback system like this can avoid PWM sideband aliasing -- in spite of the clues I've given you about architecture and ADC sampling rate, all of which are in the published patents and papers -- then you're never going to get it.
You said (many posts back) that the problem with DDFA was "the feedback". This is completely missing the point, "the feedback" -- done correctly -- is precisely the reason *why* it works.
And I'm not advertising anything; there are other feedback-type PWM systems around which may be as good, but I'm only talking about the one I have detailed knowledge of.
What I am doing is providing evidence as to why your "feedback is bad" posting is demonstrably wrong. If you don't believe me, go and measure (and listen to) the NAD amplifier 🙂
I mentioned that in general meaning. DDFA is a general abbreviation of Direct Digital Feedback Amplifier and doesn't mean the Zetex ZXCD series. It means that in a DDFA the feedback is the real deal and has to comprise some innovation to get good performance, because of the sampling of wideband output signal.
I think many people know how a Sigma-Delta DAC works. I really didn't see neither patents nor papers about ZXCD. I only understand the operation in frequency plane and imagine the functions in pictures in a few minutes, and make "simulations" for myself.
As I understand (without exact knowledge from patents and papers) basically the ZXCD works with a Sigma-Delta control-loop structure and uses a high-performance DAC to make clean reference audio signal for the error signal determination. This has the benefits of no digital filters needed inside the chip for this noise-shaping purpose and very clean reference audio signal can be reached. Then the error signal is integrated by an analog integrator which can suppress the out-of-audio band artifacts (e.g. PWM) wideband and assures the differentiator characteristics of the overall amplifier output noise-spectra. Then this error signal is sampled directly with 1-bit resolution, like it would be a digital signal, at the PWM clock frequency or higher (this is what I'm not sure about because then the power supply noise can disturb the input pad and can do amplitude modulation on the fed-back signal. Once I've considered to try this structure in FPGA but this was the retention for me from doing that. Probably in a mixed-signal IC it can be avoided. And an experienced Chip Designer is needed to design that chip, who can hold the clock jitter in ps range and have already designed the best mixed-signal ICs on the planet). Then this 1-bit sampled input can be decimated for a digital regulator. And for the best performance a very high slope PWM output is needed in order to keep the output clean from harmonics caused by the rise and fall times. This PWM also has to be fed by a stable and clean clock to avoid the intermodulation of clock jitter. I think these are the key features and most of these are about the feedback. This is why I wrote that the feedback is the real deal in DDFA.
As you are one of the designers, may I ask you some technical questions? I wrote that I think (without any information) ZXCD applies Sigma-Delta control structure. If it's right, how did you equalize the transfer functions of the two feed-in path (one to the reference DAC and the other for the PWM after the regulator) to the output? Could you post some link where the bode plots of the overall system can be found?
I think the ZXCD is a very interesting and pioneer great performance audio chip. But It can only be used for a standalone fed-back modulator like TI's TAS series and it can't be developed or modified by diyers for a better performance because its analog-related drawbacks (e.g.: It's a mixed-signal chip which can't be diy-ed).
I would prefer to have here at diyaudio.com such an all-digital design, an RTL code or something, to be shared that could be downloaded to a configurable harware by anybody on his diy-ed PCB, and could perform at a similar performance level as ZXCD. Then anybody could make a little PCB with configurable hardware and feedback ADs and download his own fed-back digital amplifier core into that and get a similar performance all-digital amplifier much cheaper than ZXCD. The RTL code could be modified by anybody. Anybody could add new functionality or modify the existing ones as he would like to do. And on this way everybody could be introduced to the design of digital logic, digital signal processing, PCB design and analog electronics, and everybody could learn about many design support tools for digital logic and digital signal processing. I think it would be a great improvement for diyers and would give much encourage for young students to develop on these fields what is a common world economy interest.
The entry functionalities of this shared code could be e.g.: dead-time control, duty-cycle limiting for short circuit protection, equalizer, dinamics compression, crossover, 8 S/PDIF inputs, 8 I2S inputs, USB input, Ethernet WEB-page and LCD for settings. I think such a design could fit in a 1 - 1.5 M gates configurable hardware, and everybody could use it, modify it, develop it, and add more functions for free. Of course simpler ones with less extra but same performance level could fit in a few hundred k gate hardware what costs about a few dollars and could give ZXCD-like performance with diy capability.
Gyula said:
Unfortunately I can't give any more details about how the DDFA feedback path works because it's Zetex's IP -- there are clues in the patent, but nothing about exactly how the feedback and especially the ADC is realised, though I can think of several ways of doing this (apart from the one that I know Zetex actually used 🙂
All I can say (because it's in the AES paper) is that the ADC sampling rate after the error integrator is the same (108MHz) as the digital PWM modulator clock frequency, and this is the key to getting the performance including all the effects from edge slew rates and dead time. The high ADC sampling rate means that the feedback loop is then fast enough to give very good power supply noise rejection. The AES paper describes some of this here
http://www.aes.org/e-lib/browse.cfm?elib=13968
but it's not free; I have a pdf at work but it's too big (220kB) to add as an attachment. The original UK patent with more info is here
http://v3.espacenet.com/searchResults?locale=en_GB&PN=GB2419757
The reference DAC is also noise-shaped PWM but with very clean edges and low jitter, this has to be better than the overall amp performance needed (>120dB SNR) so this does need a very clean supply, obviously it can't reject its own reference noise.
Of course it would be nice for DIYers if how all this worked was made public -- but it would be even nicer for Zetex's competitors who can't achieve the same level of performance, which is why I somehow don't think it will happen...
Ian
P.S. If you think these ADC sample rates and jitter requirements are challenging have a look at www.chais.info ;-)
I have checked the patent. I think my assumption was right about the Sigma-Delta control structure. But I think the reason for the high PSRR is that there are dozens of integrators in the open-loop. The PSRR depends on the open-loon gain at the PSU's disturbation frequency and that can't be set to an arbitrary high value because of the cutoff-frequency. I have also designed an all-digital amp. more than 1 year ago and I applied PSU voltage feed-forward with one more ADC to overcome this issue, and I cancelled the aliasing on a different way.
So I think the ZXCD is a great chip, maybe it could be a perfect solution for an all-digital high-power amp. But I would apply less duty-cycle modulation range than 100% and dead-time control input and duty-cycle limiting input for short-circuit protection. I think these are also key features for a commercial chip.
Gyula said:
You're correct that to get high PSRR over a wide band you need high loop gain; this does need multiple integrators and a high switching/feedback frequency like in the DDFA.
I think the Zetex chip applies all those techniques you quote -- the maximum modulation range is somewhat less than 100% (I don't say by how much) with various types of clipping control in the DSP, I believe the dead-time control is adaptively set to get optimum performance/loss tradeoff (rather than being user-adjustable), and it can not only do short-circuit protection but also measurement of loudspeaker impedance (see their other AES paper).
The only problem with DDFA for very high power amps (kW) is the high switching frequency, which makes it more difficult to get very high efficiency compared to other amps switching at 400kHz or so.
Oh, and the fact that it's only available to OEMs :-(
I have never understood the reason for an "all digital" class d amp. For me it seems much more straight forward to just combine a DSP with an analog class d amp in order to get the filtering and processing features. Adding an integrator around a globally modulated class d stage gives just as good performance at a fraction of the complexity. The DSP can have a much lower processing power.
Now, I am truly analog. I do not understand all the sampling theories etc. but my gut feeling is that the best that can be achieved is close to an analog amplifier. The only real advantage I see is that the switching frequency is constant. In a self oscillating topology the drop in frequency when increasing the output signal reduces the loop gain and also lowers the possiblity for the integrator to act effectively. But still, our analog amps perform just as good as the Zetex amps and they are really cheap.
Now, I am truly analog. I do not understand all the sampling theories etc. but my gut feeling is that the best that can be achieved is close to an analog amplifier. The only real advantage I see is that the switching frequency is constant. In a self oscillating topology the drop in frequency when increasing the output signal reduces the loop gain and also lowers the possiblity for the integrator to act effectively. But still, our analog amps perform just as good as the Zetex amps and they are really cheap.
I think there are only real advantages if you're an IC manufacturer who can do this on a very large scale.
Regards
Charles
Regards
Charles
But the cost for developing and manufacturing an IC with millions of parts inside is very high. In the end the audio business (which is very cost sensitive) is not likely to be able to buy it in high quantities?
Still a mystery.
Still a mystery.
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