Why do we need I/V stage for AD1865

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Further info re AD1865/i2s - from here:

DAC doesn't have I2S input, which is usual. It has individual data inputs for left and right channel and individual "latch" inputs which rewrites data from internal register to DAC output. Input data in I2S format (left justified) are first delayed for 13 bits thus that after shifting of 18 most significant bits to the dac register they will be written to output. For simultaneous playing of left and right channel we must delay data of left channel for 32 clocks (frame lenght for one channel). Result is that data for left and right channel are shifted together to the dac and they are written to the output with common latch signal. Because there doesn't exists 32bit shift-register I had two choices. Create them with help of Xilinx, but I have not experience with it or assemble them from easily available 8bit shift-registers. I wanted to avoid variant with registers train. However prototype with CMOS 64bit register CD4517 doesn't work thanks to different logic levels. On the end I had to use plenty of 74HCT164 which have 13 bits delay function and 32 bit register for left channel data. Result exceeded my expectations and DAC is fully functional for signals up to 192kHz/24bit which is 12.288MHz clock frequency.
 
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