Ah, no. There is primitive error detection but no provision for retries. (From the Swenson article)
I did wonder about the statement in the 6 moons article, but I didn't see any particular reason to take issue with it at the time. The general technical standard of the article and the specific assertions about the buffer dimensions led me to pass it by. I just decided that without detailed knowledge of the structure of the device he was describing it was impossible to dismiss what he had said.
'it is possible for the order of packets to be disrupted by other USB packets. In other words, a FIFO large enough to hold at least two packets is required to deal with the possible change of order. In the case of dealing with 48kHz/16-bit stereo data, the buffer capacity must be at least 48 x 16 x 2 x 2 = 3,072 bytes...'
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Edit: that should probably read 'FIFOs large enough to hold at least two packets', but it is translated from the Japanese.
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Hello
Do reclocking only the BCK, could made it out of phase with WS and DATA signals causing bits droppings ?
I already have a SAA7220 digital filter and I may use it, but even with a clean separate power supply, it's a jittery chip and it really need a reclock.
At least the WM8804 do have less jitter, and I may use this one or the DIR9001.
For me, doing a PLL are out of my knowledges.
Thank
Bye
Gaetan
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No, no problem so long as the jitter is only a small portion of the bit time. If BCK is 3MHz say then we'd need jitter approaching 300nS to get phase problems.
By coincidence, I heard a SAA7220/TDA1541 DAC last week. It was one where the SAA7220 can be bypassed. The sound was substantially better with it bypassed - much less sibilance, more perceived depth. So I can't recommend that filter chip - yes its a supply hog (stone-age lithography) but it also has really poor stop-band peformance (read aliasing problems). I also wonder if they used dither internally.
The Wolfson SPDIF receivers are widely regarded as the best of the bunch.
Can you elaborate how will be "reclocking" like that (async) of the BCK will work in the case that the frequency are different (NOT using a PLL loop to lock the two signals), even if that difference is minute?
You will skip/repeat samples periodically - a few times per second at least...
You will skip/repeat samples periodically - a few times per second at least...
No I can't because no it doesn't work when the frequencies are different. And yes, it will skip or repeat samples.
Then why did you tell him that is "No, no problem "?
He did say that a PLL is not what he wants, my guess is that he just wants to feed a xtal generated BCK directly to DAC, instead of the one coming from transport (included in the i2s).
He did say that a PLL is not what he wants, my guess is that he just wants to feed a xtal generated BCK directly to DAC, instead of the one coming from transport (included in the i2s).
Because it is no problem for the setup he's described. If you go back and review his original posting, he mentioned that he's using an SPDIF receiver. That's a chip like a WM or a DIR or a CS which contains a PLL. The BCK signal coming out of such a chip is already locked to the input stream.
Again I think you've misread him - he's saying that designing a separate (secondary) PLL to reduce the jitter beyond that from the SPDIF receiver's PLL is rather beyond him.
Out of phase for me means it is comming from a separate xtal, not extracted by the receiver cip.
😀 Well... maybe he ca clarify that.
Hello guy's
Yes, the SAA7220 do have a really poor stop-band peformance, but I'm not sure that it can worsen so much the sound. Btw, I also remember that Juaneda say that a digital filter with less taps do sound better.
I have few TDA1541A that I've buy in the 90's, so I can do experiments with them.
The SAA7220 do really need to be reclock to sound ok, some even slave the receiver and reclock the digital filter and the dac withe same xtal clock to get better sound, like in the schematic I post here, the SAA7310 can be raplace by a better receiver but I think it need to use a 11.2896 mhz clock. I would like to use a WM8804 but this one need a 12mhz clock in hardware mode.
What do you think of this schematic ?
Thank
Bye
Gaetan
Yes, the SAA7220 do have a really poor stop-band peformance, but I'm not sure that it can worsen so much the sound. Btw, I also remember that Juaneda say that a digital filter with less taps do sound better.
I have few TDA1541A that I've buy in the 90's, so I can do experiments with them.
The SAA7220 do really need to be reclock to sound ok, some even slave the receiver and reclock the digital filter and the dac withe same xtal clock to get better sound, like in the schematic I post here, the SAA7310 can be raplace by a better receiver but I think it need to use a 11.2896 mhz clock. I would like to use a WM8804 but this one need a 12mhz clock in hardware mode.
What do you think of this schematic ?
Thank
Bye
Gaetan
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That's what I did understand before.
That you will try to use a separate clock for the SAA/TDA and have in the same time a digital receiver like WM8804 to accept the SPDIF. And therefore you probably want to "feed" the DAC with two lines coming from the SPDIF receiver (DATA and WCLK) and one from the local clock (the BCLK).
It doesn't work. All what the receiver does with the local clock is just "sensing" the incoming datarate to be raported further to a DSP. But the I2S is still locked to the incoming signal by the internal PLL loop.
The clock from inside the transport will be different from the one on your DAC board. And you will skip/double samples periodically.
Unless you use some ASRC (not a great solution) or some buffer memory (written with incomming clock and read with your stable clock).
That you will try to use a separate clock for the SAA/TDA and have in the same time a digital receiver like WM8804 to accept the SPDIF. And therefore you probably want to "feed" the DAC with two lines coming from the SPDIF receiver (DATA and WCLK) and one from the local clock (the BCLK).
It doesn't work. All what the receiver does with the local clock is just "sensing" the incoming datarate to be raported further to a DSP. But the I2S is still locked to the incoming signal by the internal PLL loop.
The clock from inside the transport will be different from the one on your DAC board. And you will skip/double samples periodically.
Unless you use some ASRC (not a great solution) or some buffer memory (written with incomming clock and read with your stable clock).
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Gaetan,
Just an FYI - the number of taps in digital filter don't determine the stop-band attenuation. The precision (word size) of the coefficients does.
Just an FYI - the number of taps in digital filter don't determine the stop-band attenuation. The precision (word size) of the coefficients does.
Hello
Ok, I presume that WM8804 won't work with my reclock schematic but what about the CS8414 ?
Btw, my very first question was about reclock in general, but I did post another question with a schematic.
Thank
Bye
Gaetan
Ok, I presume that WM8804 won't work with my reclock schematic but what about the CS8414 ?
Btw, my very first question was about reclock in general, but I did post another question with a schematic.
Thank
Bye
Gaetan
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All of the receivers work in the same way. They lock into incoming SPDIF signal in order to extract the embedded clock.
Hello
So, since I can't do myself a PLL, I still have the classic reclock between the digital filter and the dac chip. Maby only reclocking BCK. Not a perfect solution but it should improve the sound ?
Thank
Bye
Gaetan
So, since I can't do myself a PLL, I still have the classic reclock between the digital filter and the dac chip. Maby only reclocking BCK. Not a perfect solution but it should improve the sound ?
Thank
Bye
Gaetan
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I did say (like three times), you cannot "reclock" just what you like. All three signals on the i2s bus are syncronous and need to remain like that all the way to the DAC.
Changing only the BCK will give skipping/doubling of the samples that I was discussing before.
Changing only the BCK will give skipping/doubling of the samples that I was discussing before.
Fewer taps would generally mean even poorer stop-band attenuation, other aspects being held the same. What Ken has said to you is only partially true. The main determiner of filter length is the width of the transition region in cases like this where the stop-band target (-60dB) is well above the quantization noise. If we start aiming for -90dB or so stop-band then coefficient quantization comes to the fore.
Its not doing reclocking because the '157 is a mux, not a latch. You wanted reclocking? Also in NOS mode, I'd want the SAA7220 not drawing its 180mA typical supply current 😉
Yeah - they do a nice reclock but then blow it totally by using OP27 in the I/V stage. I can't think of a worse choice at the price 😱
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