JoshK said:How does one model an LCLCL in PSUDII? It won't let me end with an L.
No, because few power supplies are terminated that way. Just use the minimum sized cap for the final C - 10nF and your simulation will be very close.
Sheldon
Just updating this thread with a new circuit which I'm listening to as I write. I've been using SIC diode bias recently and so applied this to the 10Y. I currently have a 15mA plate choke in it passing 12.5mA, but will replace this with a 40mA plate choke and put 20mA through the 10Y. Sounds good, as you'd expect.
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Nice Andy. Any comments on the SiC filament bias vs the previous arrangement? Sound changes?
Anthony
Anthony
SIC diode bias seems to give increased clarity and detail. Maybe just a touch sharper sound but the trade-off is worth it I think. Since it's not filament bias it's a bit easier on the filament supply. I still use choke input, though.
I had just assumed filament bias, but looking at the diagram that is incorrect. Are you planning to try filament SiC bias Andy?
I've some VT62 tubes here that I plan to try in a single stage DHT pre at some stage.
I've some VT62 tubes here that I plan to try in a single stage DHT pre at some stage.
Are you planning to try filament SiC bias Andy?
I should! At some point no doubt.
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