VRDS10 digital output tweak

[stef1777]

Hi!

I've an old 10 years VRDS10 and I'm changing some old caps for new one (power supply and coupling/decoupling caps first). I use it only as drive.

I've a question concerning the digital output.

I've found in the digital output circuit an 0.47UF + 100nF caps used to couple signal to the next stage. Do we have a way to improve this or not? What's the best? Just change the 0.47UF for a new one or another solution?

I've enclosed the schematic and wrote a red circle to show.

Thanks for your help and ideas.

 

[lucpes]

IMO it's safe to replace with a single 0.47uf film capacitor (WIMA MKP), check for the distance between the holes in the board before you buy it.

 

[stef1777]

The PCB est standard. Most the hole are 5mm. The problem is more W.

I'm not sure that 0,47UF exist for MKT or FKP series.

We can may be replace both 0.47UF and 0.1UF by an unique 0.1UF polypropylene caps? I'm thinking to MKP1837 serie from Wishay.

 

[lucpes]

Here's a good search engine: Farnell UK website search for 0.47uf

You want to know if you can replace 0.47uf+0.1uf with 1uf I suppose... Either 0.47uf alone or 1uf will do.

 

[stef1777]

The UK Farnell search engine is realy great. We don't have this in the French site (who is slow too).

Unfortunaly, a 0.47UF polypropylene caps from Wima MKP4 is realy too big to fit, and I'm not sure that this kind of caps is occurate to couple digital signal.

Wishay MKP1837 stop at 0.1uF and Wima FKP2 at 10nF.

 

[Guido Tent]

Hi

Forget about upgrading this path

Buy a new clock and apply reclocking at the digout of the CDX2500 processor

cheers

 

[stef1777]

Hi

Forget about upgrading this path

Buy a new clock and apply reclocking at the digout of the CDX2500 processor

cheers

I was thinking to you and your cristal at 26€... I was on your web this morning. Unfortunaly, I'm not quite ready to spend 150€ to offer a new complete clock board to my old VRDS10.

Just to know.

I've see on the XO3 version a "clock output". Is it something as a master clock? I have an DEQ2496 from Behringer. This unit have a master clock input. Does, the XO3 clock output will work with that?

 

[A 8]

You don't need to spend 150€ to reclock spdif. You can build your own reclocker.
Get a flipflop, separate buffer and connect the current clock, you don't even need a board as it could be hardwired.

 

[Elso Kwak]

Hi!

I've an old 10 years VRDS10 and I'm changing some old caps for new one (power supply and coupling/decoupling caps first). I use it only as drive.

I've a question concerning the digital output.

I've found in the digital output circuit an 0.47UF + 100nF caps used to couple signal to the next stage. Do we have a way to improve this or not? What's the best? Just change the 0.47UF for a new one or another solution?

I've enclosed the schematic and wrote a red circle to show.

Thanks for your help and ideas.

Hi Stef,
You can build this tranformerless interface. If you want a transformer it can be placed at the DAC-end before the comparator. Both the Scientific Conversions SC944-05 and the Pulse Engineering PE-65612 work well.
Any reclocking should be placed after the Digital Inputreceiver or in case of a digital filter after the latter as these are the main sources of jitter if you have mastered to control the reflections in the cable.😎

 

[Elso Kwak]

SPDIF reclocker

You don't need to spend 150€ to reclock spdif. You can build your own reclocker.
Get a flipflop, separate buffer and connect the current clock, you don't even need a board as it could be hardwired.

Hi A8,
My experiments did show that reclocking the SPDIF output with the masterclock of the CDP produced no improvement.
But of course YMMV...........

 

[A 8]

Well, it depends on the clock and other things.
If he wants to do it really right he should ofcourse make sure the master clock is a good one.

 

[stef1777]

What is the advantage to use an opamp to "clean" the spdif signal instead of the passive way used in the VRDS?

Stef...

ps: resolution of mister Kwak's schematic is low and values are difficult to read. 😉

 

[Elso Kwak]

What is the advantage to use an opamp to "clean" the spdif signal instead of the passive way used in the VRDS?

Stef...

ps: resolution of mister Kwak's schematic is low and values are difficult to read. 😉

Bonjour Mr. Stef,
If you enable your email I can send you a higher resolution schematic.....Or better just email me and I will reply with the schematic attached.
🙄
The opamp is not to "clean" the signal but to have a low output impedance, ideally zero Ohms, before the 75 Ohm terminating resistor and to have sufficient "drive".😎

 

[Elso Kwak]

Masterclock

Well, it depends on the clock and other things.
If he wants to do it really right he should ofcourse make sure the master clock is a good one.

Hi A8,
Of course the masterclock is the most important. That's why I concentrated on that.
You can download the schematic here:
http://www.diyaudio.com/forums/showthread.php?postid=199928#post199928

😎

 

[Elso Kwak]

Seducing Jocko

Hi,
Or you could seduce Jocko to build the SPDIF receiver in this post:
http://www.diyaudio.com/forums/showthread.php?postid=428580#post428580
This really seems to be a non-plus-ultra design with a propietary circuit.
All the hints that are used in my circuit came from Jocko and Fred.

 

[stef1777]

Bonjour Mr. Stef,
If you enable your email I can send you a higher resolution schematic.....Or better just email me and I will reply with the schematic attached.
🙄
The opamp is not to "clean" the signal but to have a low output impedance, ideally zero Ohms, before the 75 Ohm terminating resistor and to have sufficient "drive".😎

Email activated. May be default was off!

Ok, I better understand now. This solution is less expensive than to use a digital transformer. I used Lundahl transformer in the past but I was not really happy with them.

I've already downloaded the kwak-clock-7 package. The design is really great. I'm just afraid to build it as no PCB available. This kind of "high frequency" circuit are not easy to manage with a veroboard, and build a good working PCB worse.

Sorry if I go back to my original question: replace the 0.47UF and the 0.1UF caps with an unique 0.1UF polypropylene caps will work or not?

 

[Elso Kwak]

Yes

Sorry if I go back to my original question: replace the 0.47UF and the 0.1UF caps with an unique 0.1UF polypropylene caps will work or not?

Yes, it will work I believe.

 

[Guido Tent]

Re: SPDIF reclocker

Hi A8,
My experiments did show that reclocking the SPDIF output with the masterclock of the CDP produced no improvement.
But of course YMMV...........

Elso, others,

The results of SPDIF reclcoking depend on

- Initial quality of clock
- Initial quality of SPDIF
- new quality of SPDIF
- Quality of Dflipflop (family, maker)
- Quality of power supply
- Sensitiviy of DAC following SPDIF

Could you, Elso, explain about the experiments you did ?

I have not yet met a DAC that did not bennefit from upgrading SPDIF, read also test on TentLabs cllocks in Dutch HVT of last June where even a chord DAC was happy with XO3.

And I still believe a TEAC is worth to spend few bucks on 🙂

cheers

 

[stef1777]

Re: Re: SPDIF reclocker

And I still believe a TEAC is worth to spend few bucks on 🙂

Indestructible !

 

[Guido Tent]

Re: Re: Re: SPDIF reclocker

Indestructible !

got a VRDS10 in my lab an a T1 in the living room........