For a CFP VBE, I'm wondering if two caps isn't asking for trouble since together they potentially create 180° phase lag. I should think one ~big by-pass cap is best, or the combination of a larger and small cap in parallel. The bias resistor between transistors may also be important in setting the pole of the second transistor. I am not impressed by designs that claim to be high quality because they spent a lot of money on exotic parts.
It seems I've seen electrolytic caps often used in this position. Is a ceramic cap just a way to reduce the footprint a bit further?
I was reading your Ovation NX writeup and it looks like you specify a 10µF cap in that design (C14 - with a comment that its a bit oversized). I don't understand this vs your comment above. Could you elaborate further to help me understand?
Thanks Andrew!
I think when that was designed about 8 yrs ago, I had used 1uF across the bias spreader and then later went to 10 uF.
It’s stock standard 10 uF low voltage (6.3 to 10 V) XR7 MLCC