Using 0V as the inner rail to improve SOA in a pseudo class G setup?

Just a silly thought, but given that second breakdown is usually an issue with difficult loads, is there maybe something to be said for operating in class G but with the inner rail set to zero V?

The idea is that you could have the output stage run with only say 5V across it, and hence get away with only say 2 pairs of transistors, with the steering diodes connected to 0V so that when in third quadrant the transistors would not see a large supply voltage, the outer transistors then also only need to handle half the total supply (and will be the ones dissipating all the power, but a transistor that only ever sees 70V across it has way more SOA margin then one seeing 140V.

When in first quadrant the outer transistors will of course be burning essentially the same power they would in a conventional class AB stage, the savings come in Q3 when the output is supplying current while trying to pull the terminal voltage the other way,

Just a thought.