I'm working on a project with with multiple 9018 DACs run from I2S.
If I'm not mistaken, the DAC implementation I'm working with is only capable of managing LSB or MSB justification, but not both. It also doesn't have a global clock for synchronization.
If I don't use a global clock, how much an error should I expect on the high side in terms of one dac producing sound out of time with the other DACs.
If anyone has relevant search phrases so I can educate myself on this, that would be much appreciated.
If I'm not mistaken, the DAC implementation I'm working with is only capable of managing LSB or MSB justification, but not both. It also doesn't have a global clock for synchronization.
If I don't use a global clock, how much an error should I expect on the high side in terms of one dac producing sound out of time with the other DACs.
If anyone has relevant search phrases so I can educate myself on this, that would be much appreciated.
IIRC, In terms of frequency, Word clock = LRCLK = Frame Clock. Some professional audio gear can use Word Clock for synchronization. In that case Word Clock is a 75-ohm low impedance signal sent over coaxial cable, or somewhere around a 120-ohm balanced signal over AES cable. The end of the line needs to be terminated with a resistor of the same value as the cable characteristic impedance.
EDIT: More info here:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.200.7351&rep=rep1&type=pdf See Annex B
Also, there are three format settings involving justification, Left, Right, and IIS. I could say more but probably better to point to something already written.
There is some useful information in this document:
http://www.ti.com/lit/an/slaa469/slaa469.pdf
Regarding running data converters (DACs or ADCs) all on different clocks, you might not notice any difference in the short term but you may find timing is starting to drift a little off between the different devices after a few minutes, perhaps within the length of one song. Or, perhaps it will take longer. Eventually they will be noticeably out of time with each other and they will require some kind of re-synchronization.
EDIT: More info here:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.200.7351&rep=rep1&type=pdf See Annex B
Also, there are three format settings involving justification, Left, Right, and IIS. I could say more but probably better to point to something already written.
There is some useful information in this document:
http://www.ti.com/lit/an/slaa469/slaa469.pdf
Regarding running data converters (DACs or ADCs) all on different clocks, you might not notice any difference in the short term but you may find timing is starting to drift a little off between the different devices after a few minutes, perhaps within the length of one song. Or, perhaps it will take longer. Eventually they will be noticeably out of time with each other and they will require some kind of re-synchronization.
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Quick update on my last post, I changed the link for info on Word Clock. Turns out the best technical description appears to be in Annex B of AES 11-2003. Took me awhile to find it.
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The DAC implementation must have a bit clock too though. Running at 64x (usually) the sampling frequency, it runs in parallel with the data-line, also running at 64xfs, and is used to clock the data, from the data-line, into the DAC itself.
The LR clock runs at fs and shows which channel the incoming data is meant for.
With regards to synchronisation, a master processor will usually output one bit-clock and one LR-clock. It will then output as many data lines as are needed, all of which are clocked to the first two clocks, and are all synchronised.
The 9018 can accept 4 separate I2S data lines, but only has inputs for a single LR and bit clock, functioning as explained above.
If you are using a single processor/DSP, before the multiple 9018s, then all of the data-lines it outputs will be synchronised to the common bit/LR clocks. If you are using separate processors then things get more complicated. What does the rest of the system look like?
The LR clock runs at fs and shows which channel the incoming data is meant for.
With regards to synchronisation, a master processor will usually output one bit-clock and one LR-clock. It will then output as many data lines as are needed, all of which are clocked to the first two clocks, and are all synchronised.
The 9018 can accept 4 separate I2S data lines, but only has inputs for a single LR and bit clock, functioning as explained above.
If you are using a single processor/DSP, before the multiple 9018s, then all of the data-lines it outputs will be synchronised to the common bit/LR clocks. If you are using separate processors then things get more complicated. What does the rest of the system look like?
I'm hoping to use a bunch of these: Breeze audio //weiliang audioES9018K2M ES9018 I2S Input Decoding Board Mill Plate DAC Supports IIS 32bit 384K / DSD64 128 -in Amplifier from Consumer Electronics on Aliexpress.com | Alibaba Group
This is the input:
I have seen other users having issues, but their english was not very good and I couldn't understand their trouble very well.
Planning to use: Audio I2S
Short answer, yes I plan to use separate processors. Unless it would add insurmountable issues, I'll be delivering the channels to fpgas from a master source over ethernet.
This is the input:
I have seen other users having issues, but their english was not very good and I couldn't understand their trouble very well.
Planning to use: Audio I2S
Short answer, yes I plan to use separate processors. Unless it would add insurmountable issues, I'll be delivering the channels to fpgas from a master source over ethernet.
I2S is a very short distance, high-frequency, non-transmission line based interface. May I ask over what distances do the XILINX interfaces work, and what distances will be involved for your DACs?
Also, hope you do not require especially high fidelity SQ. ES9018 can sound good depending on implementation, but the boards you are considering are not well implemented.
In addition, not sure if you are familiar with high speed audio transmission, but MADI is one interface sometimes used in professional systems: MADI - Wikipedia
One other thing occurs to me, if sending BCLK or MCLCK timing information over any distance jitter is likely to be a problem. Local ASRC at each DAC can sort that out, and sync can be maintained if using SPDIF or AES3 interfaces, or something functionally equivalent. However, ES9018 ASRC is audibly not as good as later 9028 and 38.
Also, hope you do not require especially high fidelity SQ. ES9018 can sound good depending on implementation, but the boards you are considering are not well implemented.
In addition, not sure if you are familiar with high speed audio transmission, but MADI is one interface sometimes used in professional systems: MADI - Wikipedia
One other thing occurs to me, if sending BCLK or MCLCK timing information over any distance jitter is likely to be a problem. Local ASRC at each DAC can sort that out, and sync can be maintained if using SPDIF or AES3 interfaces, or something functionally equivalent. However, ES9018 ASRC is audibly not as good as later 9028 and 38.
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I do not expect more than 3-4" from the xilinx to the 9018 DAC, and I haven't given thought to whether that would be an issue.
I imagine that those DACs are not the best, especially given the price, but I haven't found on a better solution yet. Any recommendations? Price is a factor, since I am trying to network 2-300 channels.
I am open to using MADI, but I think it is proprietary. Dante is better, but VERY proprietary, and AES67 is probably going to be my method for this project.
Interesting about the ASRC capabilities of this DAC. I have never built a DAC before, so I appreciate your input.
Thanks for the detailed contribution! Any recommendations on a better DAC for this sort of project? I am comfortable with working directly with a manufacturer, but I doubt that 250-500 units would satisfy many MOQ in light of the recent ISO scandals.
I imagine that those DACs are not the best, especially given the price, but I haven't found on a better solution yet. Any recommendations? Price is a factor, since I am trying to network 2-300 channels.
I am open to using MADI, but I think it is proprietary. Dante is better, but VERY proprietary, and AES67 is probably going to be my method for this project.
Interesting about the ASRC capabilities of this DAC. I have never built a DAC before, so I appreciate your input.
Thanks for the detailed contribution! Any recommendations on a better DAC for this sort of project? I am comfortable with working directly with a manufacturer, but I doubt that 250-500 units would satisfy many MOQ in light of the recent ISO scandals.
looks like the xilinx i2s spec already includes clock synchronization across between different boards.
Performance and Resource Utilization for I2S Transmitter v1.0
That would leave just downstream syncing between the i2s as a concern. Unless I'm reading this wrong, I can input AES to a handful of these boards and sync their clocks together.
Performance and Resource Utilization for I2S Transmitter v1.0
That would leave just downstream syncing between the i2s as a concern. Unless I'm reading this wrong, I can input AES to a handful of these boards and sync their clocks together.
First, in your case it would probably be a good idea to contact an ESS distributor that services your location and go through the NDA process to get a data sheet for an ES9018K2M or any other ESS DAC chip you may be considering. It is usually pretty straightforward to do.
Also, if considering ESS DAC chips there are some publicly available documents worth careful study. You can take a look here: ESS Technology :: Downloads
The 'maximizing dac performance for every budget' spells out the most important considerations about implementation.
Regarding a recommended low-cost DAC, I don't know. ESS gets a lot of publicity probably because their DACs can sound really good, but DACs in general so far as I know are very implementation dependent in terms of SQ. That is basically why good DACs are expensive, maybe other reasons too, but that is a major factor.
My interests are primarily in the area trying to achieve excellent, maybe near SOA, but not quite SOA performance at lowest cost. So, probably not the right person to talk to for identifying 200-300 DACs for a very cost sensitive project.
Right. You send them audio data to play at the rate you send it to them. That fact keeps them in sync. ESS DACs use a (hopefully) low jitter clock located right at the DAC to minimize jitter. They perform internal ASRC to resample incoming audio into into synchronization with their local clock. Otherwise, if using, say, an AK chip, you might want to use a local external ASRC chip such as SRC4392 to perform the same function as ESS DACs do.
Yes, if using multiple processor boards you will need to have one acting as a master and then synchronise the rest to that one processor.
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