What does this do?
Where would it be wired into a CD player?
Universal 1ppm CD clock + SPDIF isolator low jitter ! | eBay
Where would it be wired into a CD player?
Universal 1ppm CD clock + SPDIF isolator low jitter ! | eBay
The Xilinx FPGA may contain internal RAM configured as a FIFO buffer, enabling the complete isolation of input clock jitter by creating new and independent clock domain for the circuits which follow. It hard to say for sure simply based on the minimal description given.
If it has a FIFO then it would need some kind of PLL but no sign of a VCXO on that board. There's only one osc, its not voltage controlled by the looks of it. I tend to agree with SoNic.
We have not been given a look at the bottom of correctly, there's no RAM. the pcb. Maybe there are components on that side too.
Edit: if I interpret the function block diagram of the XC9572XL corrcetly, it has no RAM.
I would take it for what the title says: SPDIF isolator (I presume galvanic isolation) and low jitter clock, but no jitter-killer.
Edit: if I interpret the function block diagram of the XC9572XL corrcetly, it has no RAM.
I would take it for what the title says: SPDIF isolator (I presume galvanic isolation) and low jitter clock, but no jitter-killer.
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1ppm....
I'm always suspicious when offerings claim low jitter but are wawing the long term stability (=ppm) of their clocks.
Audio needs low jitter, but doesn't care for frequency deviations in the long term.
Good long term stability doesn't imply low jitter.
I'm always suspicious when offerings claim low jitter but are wawing the long term stability (=ppm) of their clocks.
Audio needs low jitter, but doesn't care for frequency deviations in the long term.
Good long term stability doesn't imply low jitter.
With a more careful reading of the function description, it appears that the board simply re-generates a cleaner S/PDIF waveform. To do this with only digital means they would need to time-slice the input S/PDIF signal, hence, I presume, the TCXO. In any case, I think it not justified for anyone to reflexively declare that the FPGA cannot play a role in jitter reduction. They can and they do form key parts of a DPLL, for example, in commercial DAC boxes. Even of the FPGA here is not being utililzed to create a DPLL.
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please visit here for more information: ( written in chinese only )
CD&CD-ROMתÅÌÍâ¹Òʽ¸ß¾«¶ÈʱÖÓ°åVIISE - Create Dream
CD&CD-ROMתÅÌÍâ¹Òʽ¸ß¾«¶ÈʱÖÓ°åVIISE - Create Dream
Unfortunately I don't read Chinese, but I'm guessing it's the same as the English text in the eBay advertisement.
Please tell us how jitter reduction is achieved.
Please tell us how jitter reduction is achieved.
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