So I've been playing with a ucd in microcap and started to wonder if the high-side fet can handle this kind of voltage swing regarding the IRFB4020PbF has a gate to source voltage of +/- 20 V, any insight into this matter or any. Feel free to ask questions 🙂
Although the absolute maximum gate-drive voltage might be 20V, it is recommended that this be limited to about 12-15V, as the stress on the gate oxide layer would be high and the insignificant benefit due from deeper enhancement of the device is not worth the risk of having a reduced overall reliability.
Besides, the gate-driver switching power dissipation is also proportional to the square of this voltage, which means that the dissipation at 20V is already double that at 14.14V gate-drive.
Besides, the gate-driver switching power dissipation is also proportional to the square of this voltage, which means that the dissipation at 20V is already double that at 14.14V gate-drive.
VGS would normally be 0V/10V-15V to avoid wasting energy in the gate drive. Whats the objective of this design? I would change a number of things:
1) Use IC half bridge gate driver
2) Different output MOSFETs IRFB4020PbF is quite old with relatively high Rdson.
1) Use IC half bridge gate driver
2) Different output MOSFETs IRFB4020PbF is quite old with relatively high Rdson.