Hi Mark, That's a nice pair for this job. Thanks.
The hFE and Early voltage are as good as my previous cascode stage but simpler 👍 .
BTW did you measure a few of yours for hFE at say 8mA?
BTW2 Is there a SMD version? Or similar? Through hole are fine by me, and many DIY here, but my PCB designer prefers SMD and may ask.
The hFE and Early voltage are as good as my previous cascode stage but simpler 👍 .
BTW did you measure a few of yours for hFE at say 8mA?
BTW2 Is there a SMD version? Or similar? Through hole are fine by me, and many DIY here, but my PCB designer prefers SMD and may ask.
Hi bohrok2610, Thanks.
They look like the same specs as the through hole, maybe better cooling in the SOT-223. But I don't need extra cooling as I'm only running at about 1mA (50mW).
BTW the FZT757 datasheet at Digikey says the Complementary NPN Type is FZT657. Is there much difference between the FZT857 and FZT657. I can source the FZT757TA & FZT857TA local here in Australia using Digikey or Mouser.
They look like the same specs as the through hole, maybe better cooling in the SOT-223. But I don't need extra cooling as I'm only running at about 1mA (50mW).
BTW the FZT757 datasheet at Digikey says the Complementary NPN Type is FZT657. Is there much difference between the FZT857 and FZT657. I can source the FZT757TA & FZT857TA local here in Australia using Digikey or Mouser.
I haven't used them so cannot tell. FZT657TA is also available from Mouser. I guess ZTX657 is actually the complementary to ZTX757.
ZTX857 MJ measured Beta at 8mA = 163 amps per amp
ZTX757 MJ measured Beta at 8mA = 90 amps per amp
Don't have any 657s and haven't ever measured any
ZTX757 MJ measured Beta at 8mA = 90 amps per amp
Don't have any 657s and haven't ever measured any
Hi All,
I plugged in the Beta values from Mark (thanks Mark) and trimmed the output voltage close to half rail volts (42.5V). Note the trim resistor R6 needs to be moved in series with the 1Meg (R20) (because I'm not using cascoding). The trim resistor is 56k (see sim cct attached). It can be calculated if the Beta of Q2 is known, as follows:
The current source Q3 is 1.16mA and flows through Q2 so its base current is 1.16mA/160=7.25uA. Since the feedback resistor R18 is 470k and the target output voltage is 42.5V and the base voltage is 1.7V so the current through the feedback resistor is (42.5-1.7)/470k=86.5uA.
Subtract base current for Q2 means the mirror needs to sink 79.25uA. Since the mirror drains 0.3uA base current from its input, the mirror input current needs to be 79.55uA.
The voltage across the bias resistors (R20+R6) is 85V less about 0.7V for the mirror input, so the resistance is 84.3/79.55uA=1.06Meg. This is pretty close to the attached sim which uses 56k to trim the output voltage pretty close to 42.5V.
So the trim resistor of 56k can be calculated fairly closely if the Beta of Q2 is known. It assumes the down stream opamp and output stage has no offset voltage. But if the offset voltage is fairly predictable then it can be included in the calculations above and a trim resistor can be chosen before powering the amp.
The current source current is faily easy to calculate if you measure the LED voltage on a DMM when the current used is fairly close to your meters test current (0.4mA on my meter).
BTW the meters diode tester current can be measured simply by connecting a 1k 1% resistor instead of a diode, so 0.4mA reads as 400mV.
I plugged in the Beta values from Mark (thanks Mark) and trimmed the output voltage close to half rail volts (42.5V). Note the trim resistor R6 needs to be moved in series with the 1Meg (R20) (because I'm not using cascoding). The trim resistor is 56k (see sim cct attached). It can be calculated if the Beta of Q2 is known, as follows:
The current source Q3 is 1.16mA and flows through Q2 so its base current is 1.16mA/160=7.25uA. Since the feedback resistor R18 is 470k and the target output voltage is 42.5V and the base voltage is 1.7V so the current through the feedback resistor is (42.5-1.7)/470k=86.5uA.
Subtract base current for Q2 means the mirror needs to sink 79.25uA. Since the mirror drains 0.3uA base current from its input, the mirror input current needs to be 79.55uA.
The voltage across the bias resistors (R20+R6) is 85V less about 0.7V for the mirror input, so the resistance is 84.3/79.55uA=1.06Meg. This is pretty close to the attached sim which uses 56k to trim the output voltage pretty close to 42.5V.
So the trim resistor of 56k can be calculated fairly closely if the Beta of Q2 is known. It assumes the down stream opamp and output stage has no offset voltage. But if the offset voltage is fairly predictable then it can be included in the calculations above and a trim resistor can be chosen before powering the amp.
The current source current is faily easy to calculate if you measure the LED voltage on a DMM when the current used is fairly close to your meters test current (0.4mA on my meter).
BTW the meters diode tester current can be measured simply by connecting a 1k 1% resistor instead of a diode, so 0.4mA reads as 400mV.
My previous Post 261 has a DC blocking capacitor on the input with a time constant in the seconds so there is negligible rolloff at 10Hz. This requires a long time for the output voltage to settle after tuning on the power like 10-20 seconds. The conventional modern amp topology does not take such a long time to settle unless a DC servo is used.
So I have simulated an alternative servo that allows a fast turn on (less than 1 second) and can eliminate the input capacitor and without a servo capacitor.
On the LHS the input stage negative supply is pulled below the negative rail by the circuit on the RHS using an opamp and a low current 5V auxilliary supply.
The bias supply opamp has a mirror bias circuit that is the same as the input stage; it relies on thermal tracking to the input stage and similar parts to the input stage. The bias supply is trimmed with R36 for zero input offset to the input stage tranistor Q2 with no input voltage (or open circuit input). Then the amps output voltage Vout1 is trimmed with R6 to half the rail voltage (42.5 here) for a symmetrical clip.
Notice the mirror circuit does not need a servo capacitor and tracks the positive supply rail voltage. This means the amps output voltage tracks the supply rail as the amp powers up (or powers down).
If the supply voltage is a split supply (eg 42.5V+42.5V) then the full output can be maintained down to 0Hz making it useful for non-audio industrial uses.
But for audio, a single supply is quite adequate down to 20Hz. With Cout1, Cout2 of 4,700uF the attached simulation shows only a 2 watts reduction at the peaks of 204W and that's with a 3Vrms variation across these capacitors. These capacitors mainly provide DC blocking if the amp output goes to the rails with DC, like from a failure somewhere or some servo's DC offset from the source (since there's now no need for a capacitor on the input for biasing). An input capacitor should be added as an option to this amp.
BTW I found the previous input stage with 20k input resistor only gave a -3dB bandwidth of 45kHz so I have reduced the input resistor to 10k (and halved the feedback resistor to 220k and halved related resistors). This gives a 90kHz bandwidth. If the optional 150pF is connected across the input resistor then the babdwidth can be increased 400kHz. But 90kHz is enough for my likings as it provides useful suppression of unwanted RF.
So I have simulated an alternative servo that allows a fast turn on (less than 1 second) and can eliminate the input capacitor and without a servo capacitor.
The bias supply opamp has a mirror bias circuit that is the same as the input stage; it relies on thermal tracking to the input stage and similar parts to the input stage. The bias supply is trimmed with R36 for zero input offset to the input stage tranistor Q2 with no input voltage (or open circuit input). Then the amps output voltage Vout1 is trimmed with R6 to half the rail voltage (42.5 here) for a symmetrical clip.
Notice the mirror circuit does not need a servo capacitor and tracks the positive supply rail voltage. This means the amps output voltage tracks the supply rail as the amp powers up (or powers down).
If the supply voltage is a split supply (eg 42.5V+42.5V) then the full output can be maintained down to 0Hz making it useful for non-audio industrial uses.
But for audio, a single supply is quite adequate down to 20Hz. With Cout1, Cout2 of 4,700uF the attached simulation shows only a 2 watts reduction at the peaks of 204W and that's with a 3Vrms variation across these capacitors. These capacitors mainly provide DC blocking if the amp output goes to the rails with DC, like from a failure somewhere or some servo's DC offset from the source (since there's now no need for a capacitor on the input for biasing). An input capacitor should be added as an option to this amp.
BTW I found the previous input stage with 20k input resistor only gave a -3dB bandwidth of 45kHz so I have reduced the input resistor to 10k (and halved the feedback resistor to 220k and halved related resistors). This gives a 90kHz bandwidth. If the optional 150pF is connected across the input resistor then the babdwidth can be increased 400kHz. But 90kHz is enough for my likings as it provides useful suppression of unwanted RF.
Recently I bought a piece of at-the-time "high end" gear made by Threshold in 1978. It included what I consider to be an utterly brilliant piece of human-engineering: An 8-pin thru hole DIP which flashed the front panel "yes the power is ON" LED, once per second, for 30 seconds. After 30 seconds this same DIP-8 disabled the muting relays and switched from (Output = 0.00000) to (Output = Gain * Input). This allowed the Threshold design engineer to include very long timeconstants in his coupling capacitors and bypass capacitors and get-the-hell-ready-for-action capacitors. Brilliant.
Today we could do it with an $0.75 microcontroller, either surface mount or thru hole. And the best part is: the user -- the gear owner -- doesn't mind, because the flashy lighty distraction makes her forget that she has to wait 30 seconds for the music to appear. Brilliant.
Today we could do it with an $0.75 microcontroller, either surface mount or thru hole. And the best part is: the user -- the gear owner -- doesn't mind, because the flashy lighty distraction makes her forget that she has to wait 30 seconds for the music to appear. Brilliant.
Hi Mark, That reminded me of a valve radio I had when starting in electronics and I would watch the '80' rectifier tube warming up, for about 30 seconds.
Have you (or anyone) seen my mirror bias generator used in a power amplifier? I don't recall seeing it in Bob Cordell or Douglas Self's design books, nor the Horowitz & Hill's Art of Electronics. It is ideal for single rail amps for removing the input capacitor and its relatively long time constant.
A reason I wanted a short time constant for start up is the time it takes when simulating a mains power supply with my single rail power amp. It would take about 1minute for 1 second of simulation with a 1kHz input signal and 50Hz mains for the power supply. So waiting 30 seconds for the input capacitor to reach 99% of final charge was too long for me, like 30 minutes! Hence my latest method.
Here's the circuit I simulated with 50Hz mains with the bias generator and no input capacitor and the plot of start up to steadystate with 20Hz signal for just clip or 100W average:
The light green (top plot) is the 50Hz secondary mains and the dark green is Vout2 (mid-point of the power rail). The white trace is Vout3 which is generated from Vout1-Vout2 (needed to do Fourier analysis or FFT). Lower trace V(b2) is the base voltage for Q2 input transistor which settles after about 300ms once the power rail reaches 80V so clipping stops and the trace then shows the signal driving the base of Q2.
Notice Vout2 plot (dark green) tracks the rail voltage accurately at 50% as the rail voltage increases due to the slow charging of the capacitance multiplier capacitor C4. There is no DC transient in the load. Same with powering down. Nice.
A quick note on the capacitance multiplier. M1 is the main series pass MOSFET. M2 is a cascode MOSFET that shorts R1 (1 Ohms) when M1 voltage drop becomes small and the current is large. This resistor dissipates about half the power loss in the capacitance multiplier and was used (patented?) by McPherson and mentioned in an Electronics World article by Ian Hickman for a linear power supply. It halves the heatsink size for the capacitance multiplier and allows higher ripple voltages with smaller reservoir capacitor. The overall amp cost reduction is significant since the power supply capacitor is a major part of the parts cost.
I have used this McPherson idea for a guitar amp where the variable voltage pot serves well a power output control for the power amp, useful for low power level practice at home. Embarrassingly, my first version did not have D7 and R28 and the gate-source voltage can exceed the breakdown voltage during start up (since C9 is fully charged before C4) which blew M2 (with a drain-source short!). This issue was not spotted in my initial a simulation, since MOSFETs don't blow up in LTspice.
Have you (or anyone) seen my mirror bias generator used in a power amplifier? I don't recall seeing it in Bob Cordell or Douglas Self's design books, nor the Horowitz & Hill's Art of Electronics. It is ideal for single rail amps for removing the input capacitor and its relatively long time constant.
A reason I wanted a short time constant for start up is the time it takes when simulating a mains power supply with my single rail power amp. It would take about 1minute for 1 second of simulation with a 1kHz input signal and 50Hz mains for the power supply. So waiting 30 seconds for the input capacitor to reach 99% of final charge was too long for me, like 30 minutes! Hence my latest method.
Here's the circuit I simulated with 50Hz mains with the bias generator and no input capacitor and the plot of start up to steadystate with 20Hz signal for just clip or 100W average:
The light green (top plot) is the 50Hz secondary mains and the dark green is Vout2 (mid-point of the power rail). The white trace is Vout3 which is generated from Vout1-Vout2 (needed to do Fourier analysis or FFT). Lower trace V(b2) is the base voltage for Q2 input transistor which settles after about 300ms once the power rail reaches 80V so clipping stops and the trace then shows the signal driving the base of Q2.
Notice Vout2 plot (dark green) tracks the rail voltage accurately at 50% as the rail voltage increases due to the slow charging of the capacitance multiplier capacitor C4. There is no DC transient in the load. Same with powering down. Nice.
A quick note on the capacitance multiplier. M1 is the main series pass MOSFET. M2 is a cascode MOSFET that shorts R1 (1 Ohms) when M1 voltage drop becomes small and the current is large. This resistor dissipates about half the power loss in the capacitance multiplier and was used (patented?) by McPherson and mentioned in an Electronics World article by Ian Hickman for a linear power supply. It halves the heatsink size for the capacitance multiplier and allows higher ripple voltages with smaller reservoir capacitor. The overall amp cost reduction is significant since the power supply capacitor is a major part of the parts cost.
I have used this McPherson idea for a guitar amp where the variable voltage pot serves well a power output control for the power amp, useful for low power level practice at home. Embarrassingly, my first version did not have D7 and R28 and the gate-source voltage can exceed the breakdown voltage during start up (since C9 is fully charged before C4) which blew M2 (with a drain-source short!). This issue was not spotted in my initial a simulation, since MOSFETs don't blow up in LTspice.
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Hi Ian, I admit I've never seen the current mirror input biasing scheme before, the one which allows you to avoid an AC coupling capacitor on the input. Congratulations!
I wonder how well and how quickly the amplifier adjusts itself, when the two 4700uF, 100V rail splitter capacitors ("Cout1" , "Cout2") are not perfectly matched? Suppose one is 10% greater than 4700uF and the other is 10% less than 4700uF, since big electrolytic capacitors are not high precision devices. The 3.3K balancing resistors working alone, would take dozens of seconds to restore equilibrium. The 8R load resistor will pull OUT2 to a bias point a lot more quickly (about 75 milliseconds); but what will be that voltage? The capacitive divider voltage? (10% displaced from half-supply in this example?) The ideal half-supply voltage despite mismatched capacitors? I find it a bit perplexing.
I wonder how well and how quickly the amplifier adjusts itself, when the two 4700uF, 100V rail splitter capacitors ("Cout1" , "Cout2") are not perfectly matched? Suppose one is 10% greater than 4700uF and the other is 10% less than 4700uF, since big electrolytic capacitors are not high precision devices. The 3.3K balancing resistors working alone, would take dozens of seconds to restore equilibrium. The 8R load resistor will pull OUT2 to a bias point a lot more quickly (about 75 milliseconds); but what will be that voltage? The capacitive divider voltage? (10% displaced from half-supply in this example?) The ideal half-supply voltage despite mismatched capacitors? I find it a bit perplexing.
Hi Mark, Re mirror biasing shifting rail voltage. I saw this used for plotting FT versus Ic by bordodynov here (that you replied to)
https://www.diyaudio.com/community/...from-beginner-to-advanced.260627/post-7799641
He shifts the collector voltage using a BV source where I use and opamp. Same principle.
Re: splitter cap mismatch. Good question.
A simulation attached with mismatch up and down 10%. After 40ms the caps reach a peak of 85.5V total and 44.8V lower and 39.7V upper and 5.1V difference. After 300ms the capacitors reach an equilibrium due to current through the load according to the amps internal bias settings.
Not surprising, the equilibrium voltage is not easy to see, but is set in two steps as mentioned previously; first the mirror bias source with the opamp pull down the input transistors negative rail so the base of Q2 sits at the negative rail which is the input signal COM. Then the base of Q2 senses the amps output (Out1) via R18 and compares it to the rail voltage (Pos) via R20+R6 and the current mirror. The current mirror current and feedback current from R18 cancels when the amps output voltage is half the rail voltage when R20+R6 is twice R18 current.
Lastly, with amps output voltage pulled to half the rail voltage the capacitors mid V(Out2) to Neg will be pull to the same voltage as V(out1) with a time constant of T=(RL+Rout)*C which is about 130ms in the simulation, where Rout is the amps output resistance and C can be taken as 2*4700uF. The actual values are 4273uF and 5170uF or +/-450uF from nominal 4700uF. The load has a transient current peaking at 22ms of 400mA or 1.3W but is short lived and would not damage a speaker voice coil.
I did a measurement on my bench setup which has 3 pairs of capacitors in series. One pair is across the rails (C9) as 2x8mF/80V Suntan C13 caps each with 2% 3k3 resistors. This pair immediately after power up had 58.5V and 58.6V (note their mid node is floating).
The other 2 pairs were for each channel and the amps were disconnected. Once channel caps were nichnicon 3m3/100V LS(M) with 10k 5% resistors and gave 58.4V and 58.5V immediately after power up. The 3rd 'pair' were actually made from 8x1000u/63V as 2x4mF - they gave 58.0V and 58.9V.
The capacitance differences do not affect full-power output symmetry. At 97W just below clip the THD at 100Hz is 0.1717% with +/-10% caps and 0.1720% with equal caps.
So I did not find a significant variation in the pairs of caps. The amp will quickly equalises any voltage differences at power up when the load is present.
https://www.diyaudio.com/community/...from-beginner-to-advanced.260627/post-7799641
He shifts the collector voltage using a BV source where I use and opamp. Same principle.
Re: splitter cap mismatch. Good question.
A simulation attached with mismatch up and down 10%. After 40ms the caps reach a peak of 85.5V total and 44.8V lower and 39.7V upper and 5.1V difference. After 300ms the capacitors reach an equilibrium due to current through the load according to the amps internal bias settings.
Not surprising, the equilibrium voltage is not easy to see, but is set in two steps as mentioned previously; first the mirror bias source with the opamp pull down the input transistors negative rail so the base of Q2 sits at the negative rail which is the input signal COM. Then the base of Q2 senses the amps output (Out1) via R18 and compares it to the rail voltage (Pos) via R20+R6 and the current mirror. The current mirror current and feedback current from R18 cancels when the amps output voltage is half the rail voltage when R20+R6 is twice R18 current.
Lastly, with amps output voltage pulled to half the rail voltage the capacitors mid V(Out2) to Neg will be pull to the same voltage as V(out1) with a time constant of T=(RL+Rout)*C which is about 130ms in the simulation, where Rout is the amps output resistance and C can be taken as 2*4700uF. The actual values are 4273uF and 5170uF or +/-450uF from nominal 4700uF. The load has a transient current peaking at 22ms of 400mA or 1.3W but is short lived and would not damage a speaker voice coil.
I did a measurement on my bench setup which has 3 pairs of capacitors in series. One pair is across the rails (C9) as 2x8mF/80V Suntan C13 caps each with 2% 3k3 resistors. This pair immediately after power up had 58.5V and 58.6V (note their mid node is floating).
The other 2 pairs were for each channel and the amps were disconnected. Once channel caps were nichnicon 3m3/100V LS(M) with 10k 5% resistors and gave 58.4V and 58.5V immediately after power up. The 3rd 'pair' were actually made from 8x1000u/63V as 2x4mF - they gave 58.0V and 58.9V.
The capacitance differences do not affect full-power output symmetry. At 97W just below clip the THD at 100Hz is 0.1717% with +/-10% caps and 0.1720% with equal caps.
So I did not find a significant variation in the pairs of caps. The amp will quickly equalises any voltage differences at power up when the load is present.
Thank you! When you go into production, your purchasing agent will be thrilled that +/- 20% tolerance on the big ole bohunker electrolytic caps, is perfectly acceptable.
Hi Mark,
I was surprised by the size of the latest 3m3 100V caps - only 50mm long and 15mm dia!
Small compared to the "big ole electros" of the 70's when I started out building amps.
I was surprised by the size of the latest 3m3 100V caps - only 50mm long and 15mm dia!
Small compared to the "big ole electros" of the 70's when I started out building amps.
Here's a bridge circuit simulation for 8 ohms with the level shifters and a power supply. Each side of the bridge has 2 slices in parallel for 10A peak. Each side is fed by one level shift. Both sides use one bias generator -- so the 2 inputs are DC coupled. The load is also DC coupled.
The output voltage is 'Vout3' which is processed from Vout1-Vout2 to allow FFT and .Four analysis. THD is 0.2% at just clip 402W. At 4W THD is 7ppm.
The opamps gain had to be reduced to unity to stop oscillation at 20MHz when coming out of hard clip during ramp up of the power rail. Still, there's no compensation needed.
The power supply uses a 35V+35V AC transformer of 500VA. The no-load secondary voltage is 38V+38V. This gives 101V on the main capacitor with no signal and falls to 89V on the Pos rail at full output. The main capacitor has a ripple current of 9A and would best be made from two 2,200uF high ripple current caps in parallel. The cap multiplier allows a high ripple voltage and a smaller capacitor. A big heatsink (or two heatsinks) is needed with about 20W per transistor at full output -- that's about 160W of heat. But for most music listening the dissipation will be close to the idle dissipation of 11W per transistor or 80W total.
The transformer dissipates about 50W for 400W out and the temperature rise would be 50C which is acceptable for long term sinewave use into 8 ohms. But the diodes in the autobias circuit have been reduced to single 3A diodes which are only suitable for music with average power of several watts long term - for long term sinewave operation at full power dual 8A diodes should be used on a small heatsink, eg MUR1615 or similar in SMD.
It's getting close to a worthwhile project. My PCB's to make this bridge are still in progress. The level shift and bias gen will probably be on a daughter board so I can use my main PCBs for a floating supply non-bridged 100W version. The level shift and bias gen are great for bridging and/or running several amps off one single non-floating supply. The cap multiplier will probably be as a separate PCB.
The opamps gain had to be reduced to unity to stop oscillation at 20MHz when coming out of hard clip during ramp up of the power rail. Still, there's no compensation needed.
The power supply uses a 35V+35V AC transformer of 500VA. The no-load secondary voltage is 38V+38V. This gives 101V on the main capacitor with no signal and falls to 89V on the Pos rail at full output. The main capacitor has a ripple current of 9A and would best be made from two 2,200uF high ripple current caps in parallel. The cap multiplier allows a high ripple voltage and a smaller capacitor. A big heatsink (or two heatsinks) is needed with about 20W per transistor at full output -- that's about 160W of heat. But for most music listening the dissipation will be close to the idle dissipation of 11W per transistor or 80W total.
The transformer dissipates about 50W for 400W out and the temperature rise would be 50C which is acceptable for long term sinewave use into 8 ohms. But the diodes in the autobias circuit have been reduced to single 3A diodes which are only suitable for music with average power of several watts long term - for long term sinewave operation at full power dual 8A diodes should be used on a small heatsink, eg MUR1615 or similar in SMD.
It's getting close to a worthwhile project. My PCB's to make this bridge are still in progress. The level shift and bias gen will probably be on a daughter board so I can use my main PCBs for a floating supply non-bridged 100W version. The level shift and bias gen are great for bridging and/or running several amps off one single non-floating supply. The cap multiplier will probably be as a separate PCB.
I may have a blind spot, I can't find the circuitry which generates Pos9, Pos9a, Neg9, Neg9a ? Could you circle those on the schematic please? Sorry for the dumb request.
The four 9V voltage sources are top left corner.
It's quite a spread. But modular.
I did consider using sub circuit blocks, but I prefer the expanded form.
It's quite a spread. But modular.
I did consider using sub circuit blocks, but I prefer the expanded form.
The previous bridge amp had two pair of power transistors per side - total idle dissipation of 80W for max output of 400W into 8 Ohms.
For nominal 8 Ohm speakers that dip to 4 Ohms four pair of power transistors are needed to deliver the 20A peaks (since each pair is current limited to 5A for SOA reasons). With four pair of power transistors per side in a bridge the idle dissipation becomes 160W which is a bit unmanageable for a Class-AB amp that is nominally rated at 400W/8R. So to reduce the dissipation while still allowing 20A peaks I have looked at using a two level supply - effectively making the bridge operate in Class-AB with Class-G. With the lower voltage of half the previous rail voltage of 85V, about 40V, the idle dissipation is back to 80W. The circuit I have simulated is below:
D7 provides the lower voltage of 37V after the capacitance multiplier M1+M2. A second capacitance multiplier provides "lift" to 80V into a 4 Ohms test load. The lift is controlled by a BV source equation that is the greater of V(ref) and 80 times the signal voltage. I use a pink noise signal for the test. It has a peak to average ratio of around 10dB which is similar to generic music. I use about 200ms which gives a few peak of up to 1.8V for the occasional 20A peaks (1.6kW peaks) shown below as 80V peaks (green plot as V(p001).
The upper plots show the power in the capacitance multipliers. Crtl+Click on the plot to read the average powers. With pink noise just below clip of 1.6kW, the Cap Multiplier resistors R1+R2 dissipate 33W+45W or 78W average, and the average output power is 350W. The transformer dissipates 50W which is OK). But for continuous sinewaves instead of pink noise/music, this transformer cannot give the full 800W continuously into 4 ohms (just like many nominal 8 ohm amps can't). But for music just below clip it is OK for 350W average as shown above.
Attached is a simulation for the bridge with 4 pair per side for 4 ohms 20A peaks with the Class-G supply above. Caps C1,C2 have been increased to 10mF each to handle low frequency sinewaves.
The circuit is too big a spread to show here😱. Open the attachment to view the circuit in LTspice.
The top right yellow shows a peak reaching slightly over 1.6kW with about 90V lift. The lower plots is the collector current for one pair showing a 5A peak on the lower right. As shown above the 530VA transformer I modelled can handle just clip music into 4 Ohms long term. For sinewaves and 4 Ohm loads, the transformer rating would need be doubled.
The heatsink requirement for music only use into 4 Ohms appears to be 80W - same as the idle dissipation - about half standard Class-AB thanks to Class-G. The Class-G control circuit is yet to be developed.
For nominal 8 Ohm speakers that dip to 4 Ohms four pair of power transistors are needed to deliver the 20A peaks (since each pair is current limited to 5A for SOA reasons). With four pair of power transistors per side in a bridge the idle dissipation becomes 160W which is a bit unmanageable for a Class-AB amp that is nominally rated at 400W/8R. So to reduce the dissipation while still allowing 20A peaks I have looked at using a two level supply - effectively making the bridge operate in Class-AB with Class-G. With the lower voltage of half the previous rail voltage of 85V, about 40V, the idle dissipation is back to 80W. The circuit I have simulated is below:
D7 provides the lower voltage of 37V after the capacitance multiplier M1+M2. A second capacitance multiplier provides "lift" to 80V into a 4 Ohms test load. The lift is controlled by a BV source equation that is the greater of V(ref) and 80 times the signal voltage. I use a pink noise signal for the test. It has a peak to average ratio of around 10dB which is similar to generic music. I use about 200ms which gives a few peak of up to 1.8V for the occasional 20A peaks (1.6kW peaks) shown below as 80V peaks (green plot as V(p001).
The upper plots show the power in the capacitance multipliers. Crtl+Click on the plot to read the average powers. With pink noise just below clip of 1.6kW, the Cap Multiplier resistors R1+R2 dissipate 33W+45W or 78W average, and the average output power is 350W. The transformer dissipates 50W which is OK). But for continuous sinewaves instead of pink noise/music, this transformer cannot give the full 800W continuously into 4 ohms (just like many nominal 8 ohm amps can't). But for music just below clip it is OK for 350W average as shown above.
Attached is a simulation for the bridge with 4 pair per side for 4 ohms 20A peaks with the Class-G supply above. Caps C1,C2 have been increased to 10mF each to handle low frequency sinewaves.
The circuit is too big a spread to show here😱. Open the attachment to view the circuit in LTspice.
The top right yellow shows a peak reaching slightly over 1.6kW with about 90V lift. The lower plots is the collector current for one pair showing a 5A peak on the lower right. As shown above the 530VA transformer I modelled can handle just clip music into 4 Ohms long term. For sinewaves and 4 Ohm loads, the transformer rating would need be doubled.
The heatsink requirement for music only use into 4 Ohms appears to be 80W - same as the idle dissipation - about half standard Class-AB thanks to Class-G. The Class-G control circuit is yet to be developed.
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The Class-G control circuit is shown below with opamps simulating the bridged power amp
D10,D11 provide absolute value of Vout1 and Vout2.
Q1 turns off when the output voltage drops below about 2.5V, raising "Lift" voltage to the bridge power amps.
C3 is compensation to prevent ringing when the lift voltage is near maximum. R12 degeneration is needed for HF stability.
BTW the level_3a subcircuit provided in LTspice only allows an Rout of 10 Ohms for rail saturation (OK for opamps up to 100mA). So the subcircuit was modified for 20A output with an Ron of 0.1 ohms to simulate my bridge with 1.6kW output peaks.
Plots below are for the lift circuit added to the Autobias bridge amp from the previous post and with a pink noise signal:
Since the bridge circuit is too big for here, open the attached Autobias... file to view the complete amp and power supply with the new lift circuit.
D10,D11 provide absolute value of Vout1 and Vout2.
Q1 turns off when the output voltage drops below about 2.5V, raising "Lift" voltage to the bridge power amps.
C3 is compensation to prevent ringing when the lift voltage is near maximum. R12 degeneration is needed for HF stability.
BTW the level_3a subcircuit provided in LTspice only allows an Rout of 10 Ohms for rail saturation (OK for opamps up to 100mA). So the subcircuit was modified for 20A output with an Ron of 0.1 ohms to simulate my bridge with 1.6kW output peaks.
Plots below are for the lift circuit added to the Autobias bridge amp from the previous post and with a pink noise signal:
Since the bridge circuit is too big for here, open the attached Autobias... file to view the complete amp and power supply with the new lift circuit.
Hi Pawel, Thanks for all the likes over the years you have been following this thread👍. Likewise, all other followers👍.
I have posted a brief summary of the two topologies I/we have developed in this thread in my Post 1 here
https://www.diyaudio.com/community/...ching-auto-bias-power-amp.375141/post-6735925
The cleaned up sims for these two topologies - they are attached below. The 2 on LHS are for LT-XVII.
The LT-IV file differs from the LT-XVII file in the Opamp subcircuit name. Use level.3a for LT-IV and level_3a for LT-XVII and later with .lib UniversalOpamps3.sub directive in LT-XVII (but its not needed for LT-IV).
BTW These 2 amps are for voltage drive. The simpler floating supply one has only 6dB nfb, so about 6 ohms output resistance as a single slice (100W/8R).
For 4 ohms you need two slices in parallel giving 3 ohms and 200W/4R. You can use a lower rail voltage if you like, eg 50V for 100W into 4R. Both topologies can be modified for current drive. I may look into that for you😉.
I need to get the PCBs for two topologies made and tested.
Cheers,
Ian Hegglun
I have posted a brief summary of the two topologies I/we have developed in this thread in my Post 1 here
https://www.diyaudio.com/community/...ching-auto-bias-power-amp.375141/post-6735925
The cleaned up sims for these two topologies - they are attached below. The 2 on LHS are for LT-XVII.
The LT-IV file differs from the LT-XVII file in the Opamp subcircuit name. Use level.3a for LT-IV and level_3a for LT-XVII and later with .lib UniversalOpamps3.sub directive in LT-XVII (but its not needed for LT-IV).
BTW These 2 amps are for voltage drive. The simpler floating supply one has only 6dB nfb, so about 6 ohms output resistance as a single slice (100W/8R).
For 4 ohms you need two slices in parallel giving 3 ohms and 200W/4R. You can use a lower rail voltage if you like, eg 50V for 100W into 4R. Both topologies can be modified for current drive. I may look into that for you😉.
I need to get the PCBs for two topologies made and tested.
Cheers,
Ian Hegglun
Dear Ian!
You are welcome!
I deeply admire your efforts for excellent ns amp.
I wish I could drop something more than the like to make the thread more creative...
You are welcome!
I deeply admire your efforts for excellent ns amp.
I wish I could drop something more than the like to make the thread more creative...