No.
Look at any of the output stages where gain is just a tiny bit less than 1.
when the voltage margin decreases, that tiny bit less than 1 becomes an ever growing bit less than 1.
If the gain of the output stage drops, then the Aol is also dropping.
Look at any of the output stages where gain is just a tiny bit less than 1.
when the voltage margin decreases, that tiny bit less than 1 becomes an ever growing bit less than 1.
If the gain of the output stage drops, then the Aol is also dropping.
I made some sims with LTspice of a non-inverting lm3886 with a gain of 20 (20k/1k).
Input is set to 100 Hz 0.5v. As expected the Output is 10V. I can reduce the rail voltages down to 14V before the signal starts to clip. Output remains 10V.
Input set to Hz 0.5V. Capacitor 1000uF.
At 100 Hz rail is 28V
At 50 Hz rail is 20V
At 5 Hz rail is 14V
Conclusions:
Gain is linear up to an output signal 4V below rail voltage. (TI call it saturation)
When selecting Capacitors you need to take into consideration the lowest frequency you plan to send through the amp.
Hope I got this right.
Input is set to 100 Hz 0.5v. As expected the Output is 10V. I can reduce the rail voltages down to 14V before the signal starts to clip. Output remains 10V.
Input set to Hz 0.5V. Capacitor 1000uF.
At 100 Hz rail is 28V
At 50 Hz rail is 20V
At 5 Hz rail is 14V
Conclusions:
Gain is linear up to an output signal 4V below rail voltage. (TI call it saturation)
When selecting Capacitors you need to take into consideration the lowest frequency you plan to send through the amp.
Hope I got this right.
Last edited:
Absolutely right Mark. Gain is set by the input resistor and the feedback resistor and is linear until clipping.
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