The Aleph Jango

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#121
toss them to jig and see what's Ugs for 2A

then you'll know everything ; after that , everything is just simple math

every time I start forgetting how to ride a bicycle , I make another round , and everything is back

:clown:

just a general remark - regarding A CCS ; having Rs in range of 0R47 is ballpark of 1A5 Iq, per mosfet (considering governing bjt's PN constant of 0V65)

everything above 1A5 Iq is pushing the envelope

ya wanna more - decrease Rs

take a look at Babelfish J

give me 100SJEPs , will make ya 50 stereo Jango's , in a day
 

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#122
I know what you mean, but these are supposed to be matched, so the fact that they are resulting in different bias is interesting, for lack of a better word. I remember in the F6 thread, Ilquam speaking of how transistors that were matched in standard way did not necessarily yield same results. Time will tell, as you say. Round and round we go😀
 
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#131
I know. I have only read you ill one time, and that was at Andrew for being DIY bully. It makes perfect sense that 2A would have less distortion and can be easily accomplished with SS as they dont need same thermal runway protection of some fets (as shown in F6/being similar to laterals). I am not sure if this is positive tempco or negative. I do know that the Fqa are the opposite and will take off if not taken care of, and i assumed that this was reason. Changing ACS bias is matter of adjusting the Rs to .33R if you want 2A, but i wonder if FQA is stable there and with such low Rs, and also with non matching Jfet in lower half, as they do work as a bad set of twins.

edit; just saw your amendment.
 
#132
The J factor aside, the transconductance of the SJEP120R100 at 1A is about 10S, or equivalent to 0.1R.
The source resistor is 0R47, so FET + Rsource is about 0R57 per FET.

The not-yet-quite-unobtanium 2SK3497, on the other hand has a Yfs of 6S at 1A.
So FET + Rsource = 0R64.
But it has a Vgs of something like 2V+, resulting in a higher gain of the first stage (larger drain resistor value).
So overall open loop gain is actually higher with the 2SK3497.

Unless of course you lower the Rsource to something like 0R1.
Then the balance changes somewhat .....


Patrick
 
#133
I actually have some of the sk3497 matched fets that were sold early on in the F5x thread. Perhaps I will give them a try. I had planned on doubling up the input jfets to raise gain. Before i do anything, I want to test all possible fets and get some working parameters so i have some solid numbers. I was just trying to throw it together, but that never works out.
 
#135
So lower idss rated Jfets mean larger LTP Load resistor(pot for vgs adjustment)and higher gain as a result.

Doubling up Jfets does increase Yfs. What are the effects? I understand that capacitance increases with paralleled jfets, affecting(lowering)bandwidth. It also lowers noise. Does it not affect distortion profile as well, generally lowering overall distortion.
 
#137
Ha! You made a mistake. Seems you are human after all. 😀 JK and thanks for the help.
Increased Yfs basically means that a prticular transistor, in this case the jfets, are more capable of maintaning/achieveing that gain under load, correct.

Just trying to lay this out, as I think it might be helpful little bit of understanding. I understand it is available elsewhere for investigation, but sometimes it helps to be explained from the perspective of someone in the same trenches, so to speak.
 
#138
One of those very rare occasions .... 🙂
I was actually going to delete the post, but you were just a minute too early with #135.

You should think about transconductance as a hidden resistor at the source equal to 1/Yfs.
Then you can calculate the gain of the LTP accordingly.

In that sense, you can also use a single pair of FETs & reduce first stage current by half.
Your 1st stage gain will equal to that of parallel 2x JFETs.
Only the second stage bandwidth is reduced in comparison, due to the larger Rdrain.
But you get in back in closed loop due to increase in feedback.


Patrick
 
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#139
Thank you for the explanation. There was talk in another thread that in a particular case, paralleled jfets were used in the LTP of an amp, even thought the CCS was set lower as you have suggested. I would assume this would have the effect of both raising gain and making for beefier FE.
 
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