I just put together a DDDAC kit which includes a Tent XO1 clock. When I look at the waveform coming out of the clock its a very bad squarewave. There is overshoot and undershoot on each edge of at least a volt. There is also at least one cycle of .5 volt ripple on top and bottom sections. The 5V supply is very clean, it has its own battery driven regulator.
With such a precision clock I expected a better waveform. Currently the output drives one HC load, is it supposed to drive a specific impedance? I checked the Tentlabs site and there is nothing about specific terminations.
It IS working, the DDDAC produces very nice sound, but I just can't believe the clock output is supposed to look like that.
John S.
With such a precision clock I expected a better waveform. Currently the output drives one HC load, is it supposed to drive a specific impedance? I checked the Tentlabs site and there is nothing about specific terminations.
It IS working, the DDDAC produces very nice sound, but I just can't believe the clock output is supposed to look like that.
John S.
Did you use 50 Ohm series resistor at the output as suggested ? And did you try another 5V supply for comparison ?
Of course you calibrated the probes of whatever measuring device you attached before you measured overshoot.
I found several philips data books on XO oscillators. From what I gather, Guido's XO has a fan-out of 10 (standard TTL load). Rise and fall time should be 5 ns.
If all the above check out, try a standard XO you would buy in any electronics store, and try another supply. This way you can uniquely determine which is the culprit.
I found several philips data books on XO oscillators. From what I gather, Guido's XO has a fan-out of 10 (standard TTL load). Rise and fall time should be 5 ns.
If all the above check out, try a standard XO you would buy in any electronics store, and try another supply. This way you can uniquely determine which is the culprit.
John Swenson said:
John,
If you apply a 47 ohm series resistor close to the output of the XO, a 50 ohm coax and 50 ohm input impedance of the scope, the waveform should be perfect, with a risetime close to 2 ns typically
If you measure it with a normal probe, at 1 M-ohm scope input, it looks uggly.
What you see on a scope is the result of the source (XO) and the interconnect (probes, whatever).
In addition, the extra wiring and loading on the DDDAC board may affect the waveshape too, as well as the power supply. Check, check and double check.
Let me know how you proceed
regards
Thanks Guido. On the board there is about 3/4 inch between the XO and the receiving chip, do I need to put the series resistor between them? If yes is that sufficient or do I need a terminating resistor at the load? Or no series resistor and a terminating resistor?
Thanks for input on this.
The circuit actually is working but I'm wondering if its working to its fullest potential as is.
Thanks,
John S.
Thanks for input on this.
The circuit actually is working but I'm wondering if its working to its fullest potential as is.
Thanks,
John S.
John Swenson said:
John
I'd suggest a 47 ohm series R close to the XO
termination not required
Does the receiving chip has resistors at its' outputs ?
Does the XO measure correctly when probed correctly ?
regards
Speaking of the Tent Clock
Konnichiwa Tent San,
A quick question or two, if I may. I'm currently implementing the Tent Clock in a commercial Mod Package. Using Sanyo Os-Con's and a very low inductance stacked film capacitor bypass capacitor plus a modest value series resistor (27R) with some ferrite beads on the lead from a reasonably clean 5V supply works quite well and sounds rather good (and yes, I use a 47R5 build out resistor) .
However, two concerns, first the input driven by the Clock is a 3.3V Decoder IC, currently driven without level shifter. I'm sure reducing the input overdrive will help the overall performance.
Now I can get some inexpensive, rather high value resistor shaped chokes that would make a great substitution for the resistor and would provide a serious lowpass (>-8db @ 50Hz) by using minimal numbers of components (22mH Choke, 33uF Os-Con with bypass, a few ferrite beads).
The downside is a pretty high DCR with my preferred part, which would drop the supply voltage to the Xo appreciably below the required 5V. In some ways that would seem desirable, as it would reduce the overdrive to the input of the Decoder chip.
So, any comments? Does the XO work at lower supply voltages without significant performance degradation? Otherwise, should I worry about 5V vs 3.3V logic?
Sayonara
Konnichiwa Tent San,
A quick question or two, if I may. I'm currently implementing the Tent Clock in a commercial Mod Package. Using Sanyo Os-Con's and a very low inductance stacked film capacitor bypass capacitor plus a modest value series resistor (27R) with some ferrite beads on the lead from a reasonably clean 5V supply works quite well and sounds rather good (and yes, I use a 47R5 build out resistor) .
However, two concerns, first the input driven by the Clock is a 3.3V Decoder IC, currently driven without level shifter. I'm sure reducing the input overdrive will help the overall performance.
Now I can get some inexpensive, rather high value resistor shaped chokes that would make a great substitution for the resistor and would provide a serious lowpass (>-8db @ 50Hz) by using minimal numbers of components (22mH Choke, 33uF Os-Con with bypass, a few ferrite beads).
The downside is a pretty high DCR with my preferred part, which would drop the supply voltage to the Xo appreciably below the required 5V. In some ways that would seem desirable, as it would reduce the overdrive to the input of the Decoder chip.
So, any comments? Does the XO work at lower supply voltages without significant performance degradation? Otherwise, should I worry about 5V vs 3.3V logic?
Sayonara
Re: Speaking of the Tent Clock
Sayonara-san,
Thanks for the mail
If the logic runs at 3V3, I use a 100 ohm to 220 ohm resistive divider, instead of the normal 47 ohm output resistor.
The choke is OK, take care the circuit is reasonably well damped
I am looking into the jitter performance as function of the supply voltage
By the way, my XO contains an on board decoupling......
cheers
Kuei Yang Wang said:
Sayonara-san,
Thanks for the mail
If the logic runs at 3V3, I use a 100 ohm to 220 ohm resistive divider, instead of the normal 47 ohm output resistor.
The choke is OK, take care the circuit is reasonably well damped
I am looking into the jitter performance as function of the supply voltage
By the way, my XO contains an on board decoupling......
cheers
Re: Re: Speaking of the Tent Clock
Konnichiwa,
Will do.
I have attached the Circuit I used to simulate two ferrite beads and the choke (per datasheet) plus the 33uF Sanyo Os-Con and 10nF stacked film. All is soldered together very tightly, so the parasitics should be close.
As can be seen, any high order/frequency noise out of the supply is well suppressed, 18db @ 300Hz, 48db @ 3KHz and > 90db @ 30KHz to around 700KHz with still > 40db @ 10KHz. The one core resonance observable is that of the choke itself.
Do you think I got this close? How much capacitance with what sort of ESL & ESR is inside the clock (if you can/want to mention it of course)?
I personally simply prefer using passive circuitry to do dirty jobs, it tends to be much easier to get this right than regulators.
I'd be very interested in the results.
Sayonara
Konnichiwa,
Guido Tent said:
Will do.
Guido Tent said:
Guido Tent said:
I have attached the Circuit I used to simulate two ferrite beads and the choke (per datasheet) plus the 33uF Sanyo Os-Con and 10nF stacked film. All is soldered together very tightly, so the parasitics should be close.
As can be seen, any high order/frequency noise out of the supply is well suppressed, 18db @ 300Hz, 48db @ 3KHz and > 90db @ 30KHz to around 700KHz with still > 40db @ 10KHz. The one core resonance observable is that of the choke itself.
Do you think I got this close? How much capacitance with what sort of ESL & ESR is inside the clock (if you can/want to mention it of course)?
I personally simply prefer using passive circuitry to do dirty jobs, it tends to be much easier to get this right than regulators.
Guido Tent said:
I'd be very interested in the results.
Sayonara
Attachments
Re: Re: Re: Speaking of the Tent Clock
Is that 180pF a realistic value?
I have found that a combination of passive (Pi-filter) and active filtering (good regulator) gives the best result sonically.
Tot ziens,😕 😕 😕 😕
Goedeavond,Kuei Yang Wang said:
Is that 180pF a realistic value?
I have found that a combination of passive (Pi-filter) and active filtering (good regulator) gives the best result sonically.
Tot ziens,😕 😕 😕 😕
Re: Re: Re: Re: Speaking of the Tent Clock
Also balanced power of the CDP gives a not so subtle improvement of the sound. www.conrad.de part#514810. More on this later.
😎
Elso Kwak said:
Also balanced power of the CDP gives a not so subtle improvement of the sound. www.conrad.de part#514810. More on this later.
😎
Attachments
Re: Re: Re: Re: Re: Speaking of the Tent Clock
Konnichiwa,
Based on the chokes datasheet - yes. Note that the two Ferrite beads add a good deal of impedance at higher frequencies, where the main choke stops choking.....
Horses for courses. BTW, the LC circuit is preceeded by a LM317 Reg that provides the +5V supply for a few usually unused (and hence non-switching) IC's belonging to the "upsampling" section. So yes, it is passive filtering & reg.
I know. I am fitting a substantial Pi-Filter in the mains input (around 1KHz differential and common mode lowpass with significant value shunt/capacitive flywheel capacitors) AND use a nice little mains conditioner for the last 5 or so years, namely this one:
Steinmusic T1 Mains Filter & Balanced Power
Sayonara
Konnichiwa,
Elso Kwak said:
Based on the chokes datasheet - yes. Note that the two Ferrite beads add a good deal of impedance at higher frequencies, where the main choke stops choking.....
Elso Kwak said:
Horses for courses. BTW, the LC circuit is preceeded by a LM317 Reg that provides the +5V supply for a few usually unused (and hence non-switching) IC's belonging to the "upsampling" section. So yes, it is passive filtering & reg.
Elso Kwak said:
I know. I am fitting a substantial Pi-Filter in the mains input (around 1KHz differential and common mode lowpass with significant value shunt/capacitive flywheel capacitors) AND use a nice little mains conditioner for the last 5 or so years, namely this one:
Steinmusic T1 Mains Filter & Balanced Power
Sayonara
Guido,
I tried the 50 ohm resistor is series and got better sound and the waveform looks much better.
Thanks!
John S.
I tried the 50 ohm resistor is series and got better sound and the waveform looks much better.
Thanks!
John S.
John Swenson said:
He John, tweaks of 10$ct are always GREAT 🙂
Could you describe the sound-improvement and on a scale put the NON-reclocked sound, the sound with standard design and the plus-50Ohm option? I like to put this on my Site, so other dddac builders can improve/experiment !!
Thanks all !
doede
Hi doede,
First a little info on my system. I have a CEC TL5100Z driving an AudioNote DAC3 (old model). I ran across your DDDAC design and decided to try it. In the intervening time since I bought the kit and it arrived I was one of the ringleaders in the toshiba 3950 craze over in the Audio Asylum. For about $20 in mods it was winding up sounding very good.
When I first tried the DDDAC I noticed it sounded kind of similar to the best I got from the 3950, but with better high end air. I could not tell any difference between reclocked and straight from the DIR.
Then I tried the 50ohm resistor in series with the tent clock and now there was a significant difference. The acoustic space of the recording became alive, I couldn't tell much different in instruments or voices, but the low level ambient cues became much more obvious. In either case the music is very listenable, I have a hard time analytically listenening, I want to just go with the music. I want to get up and dance and play air banjo with the Kingston Trio!
I started poking around and realized there were no bypass caps at the chips, so I added 3 .1 uf caps in stratigic places and it increased the level of low level detail. I can still hear the difference in reclocking and straight through but both are improved.
BTW before any changes I did some jitter measurements using the indirect method, without reclocking it was pretty high (around 1000ps) with reclocking it was 80ps or so. Now its unmeasurable, the limit of my system is about 50ps so its less than 50ps. Its kind of strange that out of the box I could measure a big difference in jitter but couldn't hear any difference.
I think the design is very good and needs some more tweaks to cut down even further on jitter such as ground planes etc.
Thanks for making this available.
John S.
First a little info on my system. I have a CEC TL5100Z driving an AudioNote DAC3 (old model). I ran across your DDDAC design and decided to try it. In the intervening time since I bought the kit and it arrived I was one of the ringleaders in the toshiba 3950 craze over in the Audio Asylum. For about $20 in mods it was winding up sounding very good.
When I first tried the DDDAC I noticed it sounded kind of similar to the best I got from the 3950, but with better high end air. I could not tell any difference between reclocked and straight from the DIR.
Then I tried the 50ohm resistor in series with the tent clock and now there was a significant difference. The acoustic space of the recording became alive, I couldn't tell much different in instruments or voices, but the low level ambient cues became much more obvious. In either case the music is very listenable, I have a hard time analytically listenening, I want to just go with the music. I want to get up and dance and play air banjo with the Kingston Trio!
I started poking around and realized there were no bypass caps at the chips, so I added 3 .1 uf caps in stratigic places and it increased the level of low level detail. I can still hear the difference in reclocking and straight through but both are improved.
BTW before any changes I did some jitter measurements using the indirect method, without reclocking it was pretty high (around 1000ps) with reclocking it was 80ps or so. Now its unmeasurable, the limit of my system is about 50ps so its less than 50ps. Its kind of strange that out of the box I could measure a big difference in jitter but couldn't hear any difference.
I think the design is very good and needs some more tweaks to cut down even further on jitter such as ground planes etc.
Thanks for making this available.
John S.
Have test jitter after add 50 ohm resistor ?
I have some questions.
1. Add serial resistor will make jitter worse. Do we really need to add that resistor ?
2. What's the impact if the waveform is not good looking ?
Which is important : jitter ? or good looking waveform ?
3. Have you measure the waveform using active probe and scope with over 1GHz bandwidth ? I think a low bandwidth passive probe can't not give you the truth(real waveform).
Vincent
I have some questions.
1. Add serial resistor will make jitter worse. Do we really need to add that resistor ?
2. What's the impact if the waveform is not good looking ?
Which is important : jitter ? or good looking waveform ?
3. Have you measure the waveform using active probe and scope with over 1GHz bandwidth ? I think a low bandwidth passive probe can't not give you the truth(real waveform).
Vincent
- Status
- Not open for further replies.