Hello,
inspired by the thread TDA1540 - I2S to Offset Binary, no CPLD, no FPGA the source code for Intel Altera CPLD/FPGA devices can be found here (GitHub).
It works great connected directly to the Bravo SA9023 and to the CS8414.
Best regards
inspired by the thread TDA1540 - I2S to Offset Binary, no CPLD, no FPGA the source code for Intel Altera CPLD/FPGA devices can be found here (GitHub).
It works great connected directly to the Bravo SA9023 and to the CS8414.
Best regards
Do you think using TDA1540 without digital filter is a good idea?
The thing is it is a 14 bit dac so the quantanization noise is quite high. If I remember correctly, original Philips design uses noise shaping (dithering) to improve the SNR.
If there is need, I can add support of TDA1540 to my USB interface as well. Currently it has support for NOS dacs with 16/18/20/24 bits of resolution:
https://www.diyaudio.com/community/...put-interface-york.413504/page-2#post-7751610
Perhaps it has enough power for dithering too 🤔
The thing is it is a 14 bit dac so the quantanization noise is quite high. If I remember correctly, original Philips design uses noise shaping (dithering) to improve the SNR.
If there is need, I can add support of TDA1540 to my USB interface as well. Currently it has support for NOS dacs with 16/18/20/24 bits of resolution:
https://www.diyaudio.com/community/...put-interface-york.413504/page-2#post-7751610
Perhaps it has enough power for dithering too 🤔
I know SAA7030 did what was necessary to communicate with the TDA1540 so I ordered this from aliexpress
https://www.aliexpress.com/item/325....order_list.order_list_main.11.352e1802IJm3af
I wanted to hear the difference side by side between the two devices. My ultimate goal is to get a TDA1540 based DAC working with I2S input and a balanced analog output. The board from aliexpress with the SAA7030 ouputs an inverted signal for left and right so I'm going to try that with one miro board to make sure stereo is working, then a second to see if it'll work as a balanced DAC with 2 boards and 4 chips. If that works then I'd like to work with somebody to get the code for the CLPD device working with a balanced setup.
https://www.aliexpress.com/item/325....order_list.order_list_main.11.352e1802IJm3af
I wanted to hear the difference side by side between the two devices. My ultimate goal is to get a TDA1540 based DAC working with I2S input and a balanced analog output. The board from aliexpress with the SAA7030 ouputs an inverted signal for left and right so I'm going to try that with one miro board to make sure stereo is working, then a second to see if it'll work as a balanced DAC with 2 boards and 4 chips. If that works then I'd like to work with somebody to get the code for the CLPD device working with a balanced setup.
Philips used oversampling and noise shaping, but no dithering.
2 LSB peak-peak triangular PDF dithering (without oversampling or noise shaping) would change the requantization error from -86 dBFS distortion to a -81 dBFS noise-like signal. It sounds better when you play soft passages at a high volume setting, but it doesn't look good on a spec sheet with only SINAD values.
yes
i made few pieces all soud better than players with same dac chips but with saa and op amps
btw
the one and only dac chip that can produce clear square of 20khz. every other badly distort squares...
it would be nice to add support for 4 data outputs 14bit with emulation to 16bit
The reminder of 2 last bits 15 and 16 bits can be used for controlling the dac input data lines. At Iout will be the sum corresponds for 16 bit word. As the summ of 4 14bit words. Reminder is what number of dac chips will be supply with
I think that it can be done with Your board?
I can only have 4 data outputs. So that means 4 TDA1540 total, 2/channel.
You can't really represent a square wave with an ordinary (Nyquist-Shannon-sampled) digital signal, because it isn't band limited. For example, a sequence +1 +1 -1 -1 +1 +1 -1 -1... at 44.1 kHz sample rate represents a sine wave of 11.25 kHz with amplitude √2, as it's the only signal that is bandlimited to half the sample rate that fits through those sample points.
Sometning based on this paper
I check and it is posibile. Only the arrangements should be done before the word send to convesion.
Yes... I dont know... But I measured this at the output and with the same set up, same scope and everything else, it was not possible with other dac chips. 🙁
I cant explain why? The output was sa I am remeber, standard current injection of 2mA with BF245B, 5R (or 10R cant remember) Riv simple JFET 2SK170 gain stage with same jfets buffer,
Cdem was 820pF BUT with each dem pin with 20K R connected to -18V supply, for 0.2mA (measured) current to dem pins.
All other things was as in the datasheet and standard.
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this is 1K square
diference classic DEM C (note lower value of dem F, probaly due to 820pF C tolerance)
and free running DEM with 0.2mA additional current to dem pins, much closer to 176.x KHz
and BW 44 and 96 KHz SR
diference classic DEM C (note lower value of dem F, probaly due to 820pF C tolerance)
and free running DEM with 0.2mA additional current to dem pins, much closer to 176.x KHz
and BW 44 and 96 KHz SR
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But it need 8 pin outputs 4 pin for each channel. In praxis.
shuld be check on paper first I checked but has to be verified again...
all 4 14bit words corrected for last bit, in addition has to form a 16bit original word, and when analog outputs are summed should be emulate a 16bit word lenght value?
They do averaging in time domain. I.e. for 1 given 44.1kHz sample they send 4 words to tda1540 at 176.4kHz rate. And the reconstruction filter averages these 4 words.
As @MarcelvdG mentioned:
But it is also quite hard to call as noise shaping. As mentioned in the paper 🙂
So only 2 data lines and 2xtda1540 required for that.
Yes this is for serial 4 x OS word, BUT maybe it can be used in NOS mode in parallel words, just summing the analog products?
.
There will be one base word of 2 LSB cutout to 14bits
other 3 words are repeating in the ranfe of other 3 DAC chips...
.
Try to expand the hex word from the example?
I had it on the paper but somehow I lost 🙂
I will try again and post
Thanks 🙂
Yeah, I understand what you mean, that's why I mentioned need for 8 data lines for 8 chips (for stereo) in previous posts.
My board can't do that but it is doable with small FPGA.
However, I doubt that it will work. In principle yes but little differences between 4 DACs connected in parallel are not going to be the same as 16 bit DAC.
So averaging in time could be better approach in terms of DAC linearity.
I have this idea of laying out a board that has a footprint to plug in USB input like @eclipsevl 's board or the JL sounds board. That input would feed four TDA1540 chips. Then the board would leave the TDA1540 output exposed so someone could choose whatever output stage they want.
I'd happily pay someone to lay this out so that we could all have a board to experiment with and possibly open source so that it would continually evolve. I could stock the board and put together an assembly guide over time. I think it would be a neat project. If someone wants to help me start it, let me know.
I'd happily pay someone to lay this out so that we could all have a board to experiment with and possibly open source so that it would continually evolve. I could stock the board and put together an assembly guide over time. I think it would be a neat project. If someone wants to help me start it, let me know.
Please clarify: as I understand balanced is for one channel we need two tda1540, one gets 14 bit word as is, and another - same 14 bits but inverted: