Hi all
I am examining any possible usefullness of a switched capacitor integrator stage within the global feedback loop of a class D amplifier.
My hopes and purpose of using something like that is to kill the rippl aliasing between an amplified error signal and the carrier, which causes distortion and cannot be eaily corrected by simply more feedback.
I assume the circuit works a a sample and hold one, so that it resets and holds the value during the whole (or a half) cycle of a clock, hopefully killing the aliasing while providing lots of LF gain, I wish so anyway.
Anyone with some experience here?
Open for suggestion..
Adam
I am examining any possible usefullness of a switched capacitor integrator stage within the global feedback loop of a class D amplifier.
My hopes and purpose of using something like that is to kill the rippl aliasing between an amplified error signal and the carrier, which causes distortion and cannot be eaily corrected by simply more feedback.
I assume the circuit works a a sample and hold one, so that it resets and holds the value during the whole (or a half) cycle of a clock, hopefully killing the aliasing while providing lots of LF gain, I wish so anyway.
Anyone with some experience here?
Open for suggestion..
Adam
Usually I don't enjoy talking to myself, however I'll continue here anyway.
For what I examined the ripple aliasing is a source of distortion because modulator is a 'sample' system and the sampling takes place in a not-well-defined phase of an error-amplified ripple. Being able to 'hold' after a 'sample' operation (in a switched cap integrator or a similar s&h switched cap circuit) could integrate the ripple during a whole cycle and reset at the beginning of a next cycle.
Now, the big question is: how to determine the correct phase of sampling and correct phase of holding the error value, so that the whole stuff really does decrease distortion?
For what I examined the ripple aliasing is a source of distortion because modulator is a 'sample' system and the sampling takes place in a not-well-defined phase of an error-amplified ripple. Being able to 'hold' after a 'sample' operation (in a switched cap integrator or a similar s&h switched cap circuit) could integrate the ripple during a whole cycle and reset at the beginning of a next cycle.
Now, the big question is: how to determine the correct phase of sampling and correct phase of holding the error value, so that the whole stuff really does decrease distortion?
The phase shift or delay throught the switched capacitor network might cause problems.
I have a class d amp with loads of carrier on the output and it sounds fine.
Maybe your just being too fussy and trying to fix what the ear cant hear ?
I have a class d amp with loads of carrier on the output and it sounds fine.
Maybe your just being too fussy and trying to fix what the ear cant hear ?
Is your amp a clocked or self-clocked (ucd) design?
[backup question: how's the weather in Warsaw?😉]
Because he is talking of ripple aliasing I guess it is clocked.
For a switched capacitor integrator to actually work as such it is important that the Nyquist theorem is fulfilled. I.e. it would have to be clocked at several MHz. If not it isn't a switched capacitor integrator but some form of S&H. Which may or may not be helpful - analysis of this is not for the faint at heart.
There is a paper by Lars Risbo on loops that are minimising the ripple-aliasing effect. It can be found for free on the web. The principles are also used within the latest high-powered class-d ICs of TI.
Another variant would be the use of the so called-node transition filters.
Regards
Charles
For a switched capacitor integrator to actually work as such it is important that the Nyquist theorem is fulfilled. I.e. it would have to be clocked at several MHz. If not it isn't a switched capacitor integrator but some form of S&H. Which may or may not be helpful - analysis of this is not for the faint at heart.
There is a paper by Lars Risbo on loops that are minimising the ripple-aliasing effect. It can be found for free on the web. The principles are also used within the latest high-powered class-d ICs of TI.
Another variant would be the use of the so called-node transition filters.
Regards
Charles
The Risbo papers and may be also Cox&Candy are always a good starting point.
But unfortunately all papers that I found regarding the modulator errors focus more on the mathematical description of the issue instead of solutions.
(Well Cox&Candy even show ideas, but base on pre filter feedback.)
Assuming a clocked system with triangle modulator, you may simply step into simulation with the two most simple and IMHO most natural approaches.
a)
- Handle integration in separate from S&H. ( ==> allowing for independent parametrisation)
- Sample at pos and neg peak of triangle, or equivalent at each edge of the clock that syncs the triangle (==> sampling frequency = 2 switching frequency and symmetric lead/lag error on pos and neg half wave)
b)
- Again handle integration in separate from S&H. ( ==> allowing independent parametrisation)
- Sample at the moments of each edge of the output stage
In any case for first simulations I would use an ideal switching stage.
Sorry for not providing a bullet proof math model.
But unfortunately all papers that I found regarding the modulator errors focus more on the mathematical description of the issue instead of solutions.
(Well Cox&Candy even show ideas, but base on pre filter feedback.)
Assuming a clocked system with triangle modulator, you may simply step into simulation with the two most simple and IMHO most natural approaches.
a)
- Handle integration in separate from S&H. ( ==> allowing for independent parametrisation)
- Sample at pos and neg peak of triangle, or equivalent at each edge of the clock that syncs the triangle (==> sampling frequency = 2 switching frequency and symmetric lead/lag error on pos and neg half wave)
b)
- Again handle integration in separate from S&H. ( ==> allowing independent parametrisation)
- Sample at the moments of each edge of the output stage
In any case for first simulations I would use an ideal switching stage.
Sorry for not providing a bullet proof math model.
- Status
- Not open for further replies.