I’ve got CEC CDT with I2S and coaxial outs. While standard I2S implementation utilizes 3 wires DATA, Clock and LR Clock, CEC adds fourth wire for master clock to run CDT/DAC in master/slave mode. According to reviews CEC CDT is supposed to produce better SQ with their own ESS DAC when I2S link is used.
When it comes to jitter I2S is supposed to be a better connection than coaxial but ASCR converter in ESS DAC supposed to reduce clock jitter by converting it into random noise so IS2 connection with ESS may be redundant when it comes to jitter.
I’ve got Octo DAC 8 which is ESS Sabre DAC but I can use it with CEC CDT only with coaxial connection. I wonder if it would be any audible difference if I replace my DAC with ESS CEC DAC and use IS2.
When it comes to jitter I2S is supposed to be a better connection than coaxial but ASCR converter in ESS DAC supposed to reduce clock jitter by converting it into random noise so IS2 connection with ESS may be redundant when it comes to jitter.
I’ve got Octo DAC 8 which is ESS Sabre DAC but I can use it with CEC CDT only with coaxial connection. I wonder if it would be any audible difference if I replace my DAC with ESS CEC DAC and use IS2.
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Okay, the CEC CDT is a CD player?
I2S bus is typically in LVCMOS, or else LVDS format (LVDS uses an HDMI connector). It would be unusual to send LVCMOS between two different boxes.
I2S is usually lower jitter than SPDIF, that's correct. ASRC reduces jitter more or less by replacing SPDIF jitter noise with ASRC noise (which is hopefully lower). For ESS dacs, setting DPLL_BANDWIDTH to the minimum stable value in the control registers is recommended by ESS (it should sound better that way).
Regarding different interconnection configurations between CD transport and dacs, why not just try it an see what you like best?
I2S bus is typically in LVCMOS, or else LVDS format (LVDS uses an HDMI connector). It would be unusual to send LVCMOS between two different boxes.
I2S is usually lower jitter than SPDIF, that's correct. ASRC reduces jitter more or less by replacing SPDIF jitter noise with ASRC noise (which is hopefully lower). For ESS dacs, setting DPLL_BANDWIDTH to the minimum stable value in the control registers is recommended by ESS (it should sound better that way).
Regarding different interconnection configurations between CD transport and dacs, why not just try it an see what you like best?
CEC does not use normal I2S bus but their own Superlink which has 4 BNCs for MCK, BCK, LRCK and SD. The idea is that DAC MCK is used to synchronize the transport which sends BCK, LRCK and SD to DAC. This used to be the high-end approach for using separate transport and DAC.
Hard to say if Superlink DAC would be an audible improvement. These are expensive devices so better to try it out before final purchase decision if possible.
Hard to say if Superlink DAC would be an audible improvement. These are expensive devices so better to try it out before final purchase decision if possible.
I think that the only difference between I2S and superlink is an extra wire for MCK. I wish I could try.
Yes, but that extra MCK wire carries signal to the opposite direction (dac->transport). Nowadays in deltasigma DACs all 4 signals are unidirectional.
It does and it would make perfect sense with other DAC chips but unless I got it wrong ECC also reclock the incoming signal.
ESS offers adaptive/asynchronous resampling (ASRC) to convert the signal from incoming I2S clock to the master clock of the actual DA conversion. While their method is certainly very good, I have not seen a measurement of input jitter vs. output distortion/noise for their method. But It may exist, e.g. https://www.diyaudio.com/community/threads/hypex-ncore.190434/post-2900076 -> https://www.diyaudio.com/community/...ble-difference-whatsoever.314762/post-5290490
However, slaving the source to the DAC clock means there is no need for any ASRC as the incoming data signal is already clocked by the master clock used for the DA conversion.
Effects of none of the above are likely to be audible, but could be measurable with a good gear.
However, slaving the source to the DAC clock means there is no need for any ASRC as the incoming data signal is already clocked by the master clock used for the DA conversion.
Effects of none of the above are likely to be audible, but could be measurable with a good gear.
While CEC ESS DACs likely use ASRC for SPDIF using ASRC also for Superlink would seem quite pointless. Unfortunately CEC doesn't publish such details about their devices.
Many vendors use ESS ASRC even for async UAC2. IMO the ASRC automatic support for any incoming samplerates makes their life easier as they do not have to configure the ESS chip clock dividers for each samplerate via I2C by firmware of their UAC2 receiver - saving cost on programming XMOS. Also muting the output when switching samplerates to avoid clicks... there are a few things the constantly-running ASRC spares.