Split I2S signal between dac chips
Hi,
I am planning to build a dual-mono dac (first a stereo from usb, then a multichannel from hdmi).
My question is, how can I share the I2S signal with the 2 chips.
So here is my idea. (feel free to make constructive comments)
- There is a clock syncing everything together.
- The USB board (something from alliexpress) provides the I2S signal (which need to be duplicated somehow)
- The I2S is proccessed by 2 pcm1795 (one for each channel). These will be configured to be mono.
- Then the current to voltage conversion will be handled by 2x2 NE5534 opamps (2 for each channel)
- Finally use the pga2311 for volume control (not entirely sure about this: if i give up on dsd, then i will use the dacs internal solution)
The final version will be printed by jlc pcb.
Hi,
I am planning to build a dual-mono dac (first a stereo from usb, then a multichannel from hdmi).
My question is, how can I share the I2S signal with the 2 chips.
So here is my idea. (feel free to make constructive comments)
- There is a clock syncing everything together.
- The USB board (something from alliexpress) provides the I2S signal (which need to be duplicated somehow)
- The I2S is proccessed by 2 pcm1795 (one for each channel). These will be configured to be mono.
- Then the current to voltage conversion will be handled by 2x2 NE5534 opamps (2 for each channel)
- Finally use the pga2311 for volume control (not entirely sure about this: if i give up on dsd, then i will use the dacs internal solution)
The final version will be printed by jlc pcb.
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The fan-out of logic signals will be fine for 2-way split. If there's an MCLK (master clock), that's the fastest signal and the most crucial. You could put ~68 ohm resistors in series with such high speed signals just prior to the DAC pin to reduce ringing and reflection. (You'll see this with old computer DIMMs, the incoming signals from the connector go through such resistors).
The BCLK / LRCLK and data lines are slower and less demanding, but need to be kept in sync with each other, so they would normally be routed in parallel.
The phase relationship between these and MCLK isn't crucial so long as it stabilizes and doesn't drift relative to them. Many chips don't need MCLK and generate their own using a PLL which simplifies things.
If the PCM1795 allows a choice of which channel to use for mono only a single data line is required, or if not you can invert LRCLK for one of the chips to swap the meaning of left and right. A 74HC14 is a good chip for inverting signals at 5V, but is slower at 3.3V and 75LVC14 is preferrable then I reckon.
Keep I2S lines short, ensure every signal has ground return underneath it or alongside it or both, as with any high-speed logic trace.
The BCLK / LRCLK and data lines are slower and less demanding, but need to be kept in sync with each other, so they would normally be routed in parallel.
The phase relationship between these and MCLK isn't crucial so long as it stabilizes and doesn't drift relative to them. Many chips don't need MCLK and generate their own using a PLL which simplifies things.
If the PCM1795 allows a choice of which channel to use for mono only a single data line is required, or if not you can invert LRCLK for one of the chips to swap the meaning of left and right. A 74HC14 is a good chip for inverting signals at 5V, but is slower at 3.3V and 75LVC14 is preferrable then I reckon.
Keep I2S lines short, ensure every signal has ground return underneath it or alongside it or both, as with any high-speed logic trace.
Even on slower signals, termination resistors (like the 68 ohm you suggested) are helpful. Although all info I have seen suggest placing them close to the output pin if using series resistors.
If the rising edge of the signal is very fast then you still get the same ringing as you would with a fast signal - not as critical for that slow signal but can cause issues.
Something I am playing around with on my designs, behaviour is quite interesting.
If the rising edge of the signal is very fast then you still get the same ringing as you would with a fast signal - not as critical for that slow signal but can cause issues.
Something I am playing around with on my designs, behaviour is quite interesting.
Can someone explain how the ringing effects audio? Digital feed-thru? Mark, assuming someone is using 74 series ICs for glue logic here or elsewhere is there benefit to placing resistors between all logic ICs? I ask as someone who uses the above without resistors and am wondering if I can wring some more speed out of my custom DAC by doing so.
Values of termination resistors and the presence or absence of buffers such as 74LVC1G04 (including their location) can affect dac sound in sometimes curious ways. If curious then you might experiment around some. Otherwise, if more measurement oriented you could use a fast scope with low-capacitance active probe to adjust damping using visual observation of pulse rise time, ringing, etc. Or, if lazy just use an approximately nominal value resistor for longer traces (meaning longer than some fraction of 1/4 wavelength of the highest clock harmonic frequency) and don't worry about it.
If driving multiple lines that go to significantly different locations, NB3L553-D can be a handy chip to try.
If driving multiple lines that go to significantly different locations, NB3L553-D can be a handy chip to try.
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