yes indeed the basic spice engine is good along with some nifty extras, but the support is not quite there, as compared with pro versions like PSPICE and microCAP.
LTC spice just look at the start up name "SwCAD III"
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The documentation for LTspice leaves something to be desired; it is written for someone with some basic knowledge of SPICE. There is an LTspice users group that is very helpful. LTspice : LTspice/SwitcherCAD III
I did the sims with different power trannies..
FJL4215/4315 give the higher amplitude of oscillation,
in a continous way, not only around 0V crossing point.
MJL1302/3281 a little less, wether this is onsemi s or andy_c
models that are at work , but essenstialy the same as the
fairchild devices.
2SA1943/2S5200 produce the less, and only around the 0V
crossing point.
Frequency of sims were from 500 hz to 5khz...
Oscillation frequency is in the range of 3 mhz
depending of the power devices..
The CULPRIT is the excessive value of the lead compensation
cap C4 wich is displayed at 39pF onthe schematic..
This value is way too high, it s the first time i see such
a huge value for a lead compensation, and i think it s
perhaps a mistake on the schematic.
If you have such an amp, can you give a clue about it?...
Reducing it to 4.7pF get rid of all these problems, but i suppose
that the lag comensation cap sould be also altered, to a value of
between 39pF to 47pF...
Last , the asc file provided by PB2 show a zobel network that
consist of a 1uF cap in serial with a 5.1R resistor..
Although i find the value of the cap somewhat high, it is
of no consequence regarding stability...
So your result is some form of AM modulation? I think you said outputs running just before/near saturation ( ie Vin~2Vrms)?? What is the relationship to the input freq and levels? I thought perhaps at high dV/dt ie max freq & max Vin> was maybe breaking the loop at the VAS?
I agree the lead appears too consevative with excess phase margin from my first sims, but I don't trust the models yet. Do you know what the phase and gain margins are? Maybe the best thing is to see If any of this appears with HW tests.
Gain is only 22 , and i stated 2V pp , so that makes
about 22V peak, far from saturation..
Here the gain/phase response in closed loop of the original
amp , with nothing modified.
I used simetrix for this one, as it s a small signal analysis
that is accurate enough for gain/phase response simulation.
I don t know what is the quiescent current, so i did fix it to
140mA/power device..
That is perhaps high, so can you give me the exact value in real world?...
Bob Cordell calls the use of C4 Miller Input Compensation and he used it in his MOSFET EC amp: http://www.diyaudio.com/forums/soli...ure-phase-margin-amplifier-8.html#post2061958
In Pete's schematic, the bias is set at 44mA per device. I don't know what the recommended bias setting was, but that will effect performance to some degree. It looks like T2 is the trim pot, so varying it's value will change the bias.
I only show 15mV of DC on the output. I don't consider that a major balance problem.
I only show 15mV of DC on the output. I don't consider that a major balance problem.
Gain margin is about 12dB, phase margin is in the vicinity of 120°,
but beyond the unity loop gain frequency , the phase shift is
not proportional to the frequncy, that is, the group delay is not constant
and that will produce phase distorsion.
Here a 2khz sine with a 50nF caps added to the ouput in paralel with a 4R load with IQ set to 50mA/device.
Pete
I agree about NO caps on the output as I pointed out earlier in post #72 in this thread.
Have you changed the model and/or sims to get your PM of 80 degrees? Is there any plan to verify that with testing. The earlier plot of loop gain posted shows there are too many other poles and zeros near the unity gain cross over to say with any certainty what the PM is ie phase rate of change is very great.
EDIT> Think about it another way... hows about running the GFA_555 amp with a gain of 2? You know just for a quicky test & see if stable and what the new CL BW is?
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Hi sumaudioguy,
That statement really seems to show a lack of understanding of how an amplifier works and what determines performance. I can assure you that there are many other errors you can make in the design of an amplifier that will have a far more detrimental effect on sound quality.
Did you say somewhere that you have actually worked with amplifiers on a technical level? If so, it isn't showing. You might want to consider keeping quiet until you understand more.
-Chris
Only by a few.
That statement really seems to show a lack of understanding of how an amplifier works and what determines performance. I can assure you that there are many other errors you can make in the design of an amplifier that will have a far more detrimental effect on sound quality.
Did you say somewhere that you have actually worked with amplifiers on a technical level? If so, it isn't showing. You might want to consider keeping quiet until you understand more.
-Chris
The phase rate change is very abrupt as the second pole become
dominant at high frequencies due to the lead compensation, and this,
well before the 0db gain is reached..
With a gain of 6dB, the amp will oscillate at full swing , undoubtly..
As pointed by pb2 , making a real world test with even a slight
capacitive load would be suicidal considering the absence of
LR outpt network.
This might be the main improvement to look for for those having this amp.
The oher improvement mentionned, i.e, adding a current mirror can
be a good idea as well , but the compensation shoulfd then be modded
to accomodate the vast increase of open loop gain.
Beside, since pb2 has two units, he has the advantage of
real time comparisons in audio quality.
Anyway, it s a hard task considering the high voltages at stakes,
so if there speople willing to go that further from the original schematic,i can only wish them good luck....
infinia,
When you say you used the less accurate method do you mean the one
demonstrated in the audioamp.asc example in the Educational folder
for LTSpice?
My file is attached and I don't get the same results as your post in #18,
I used that simple method, and I didn't change the model since the last
correction.
Plot should be Vout/Va for loop gain.
Increase C3 to 4700uF in order to see the 180 deg phase of the
feedback at LF as a sanity check.
When you say you used the less accurate method do you mean the one
demonstrated in the audioamp.asc example in the Educational folder
for LTSpice?
My file is attached and I don't get the same results as your post in #18,
I used that simple method, and I didn't change the model since the last
correction.
Plot should be Vout/Va for loop gain.
Increase C3 to 4700uF in order to see the 180 deg phase of the
feedback at LF as a sanity check.
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I looked at a number of places from the threads u linked to. Talking about Prof. Middlebrook methods 2 sources and one other using a voltage source placed between the inverting input and the divider. Let me see about looking at the LT example.
EDIT> OK I have what you are reporting now.
EDIT> OK I have what you are reporting now.
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