Hello all. I realize this treatise may be riddled with errors, but may aim is to remove any misconceptions I have, so my intent is to be corrected, and if there's interest to discuss the topic at hand.
It was a revelation late in its arrival, but recently I have been switching over to looking directly at Cj parameters instead of Ft in datasheets. Why? The Ft numbers are inconsistent. The Cj parameters tell the whole story, or at least a more complete one.
If you look at the 2N5089 datasheet, it has an Ft of 50MHz. Yet Cob is 4pF. The 2N4124 has the same Cob yet is spec'd at six times the speed.
Well it mostly depends on the conditions that the transistor is tested in. With increasing Vcc, Cob decreases, which will increase Ft. With increasing current, transconductance increases, which means less dynamic voltage change over Vbe, which means less current lost through Ceb, and this again means higher Ft.
If you look closely, you'll notice that the 2N4124 is tested at 20V/10mA, and the 2N5089 is tested at 5V, 500uA. Well there's the hitch right there. The Ft if the 5089 is tested at the levels you would use it in a low noise design, because it's a low noise transistor. The 2N4124 on the other hand is a general purpose amplifier for use in switching and amplifiers up to 100MHz. So it is tested at relatively hot levels, which lend themselves to amplification and speed.
And so we get to the crux. Ft is a bad parameter to rely on. Depending on how the device is tested, you may be mislead if you don't pay attention. This is why I will be looking at Cj parameters from now on when possible.
There is another factor that limits the speed of BJT's, though I can't speak much about it. There is actually a limit to how fast the electrons can flow through the die. I'm guessing that Ft takes this into account since it is a measured value. So an argument for using the Ft parameter seems to be that even with low Cob, a transistor may still be too slow.
This is where it is helpful to look at Ft/Vce and Ft contour graphs. First look at the power limits and then at the Beta/Ic curve, and determine what your limits are for power and linear range. Then look at the contour or Ft graph to see how high you can go within those bounds.
Another consideration that begets watching Cj values is reactance. If your device is spec'd at high Ft but has gobs of Cob, it might cause stability problems for the rest of the circuit. In my opinion, lower Cj is almost always better. If another part of the circuit oscillates when a faster part is installed, I would tend to see if I can improve stability without needing to downgrade.
In all, my preference would be to try and approach the speed barrier. A limit to the speed of electrons through the junction implies, to me, something like a 2-way saturable current source, which means it will allow current to pass either way up to the limit. My reasoning is that a current source is not reactive, especially an atomic-scale current source. this implies more controlled behavior.
I have a follow up question that will come after any discussion on this.
Am I right?
- keantoken
It was a revelation late in its arrival, but recently I have been switching over to looking directly at Cj parameters instead of Ft in datasheets. Why? The Ft numbers are inconsistent. The Cj parameters tell the whole story, or at least a more complete one.
If you look at the 2N5089 datasheet, it has an Ft of 50MHz. Yet Cob is 4pF. The 2N4124 has the same Cob yet is spec'd at six times the speed.
Well it mostly depends on the conditions that the transistor is tested in. With increasing Vcc, Cob decreases, which will increase Ft. With increasing current, transconductance increases, which means less dynamic voltage change over Vbe, which means less current lost through Ceb, and this again means higher Ft.
If you look closely, you'll notice that the 2N4124 is tested at 20V/10mA, and the 2N5089 is tested at 5V, 500uA. Well there's the hitch right there. The Ft if the 5089 is tested at the levels you would use it in a low noise design, because it's a low noise transistor. The 2N4124 on the other hand is a general purpose amplifier for use in switching and amplifiers up to 100MHz. So it is tested at relatively hot levels, which lend themselves to amplification and speed.
And so we get to the crux. Ft is a bad parameter to rely on. Depending on how the device is tested, you may be mislead if you don't pay attention. This is why I will be looking at Cj parameters from now on when possible.
There is another factor that limits the speed of BJT's, though I can't speak much about it. There is actually a limit to how fast the electrons can flow through the die. I'm guessing that Ft takes this into account since it is a measured value. So an argument for using the Ft parameter seems to be that even with low Cob, a transistor may still be too slow.
This is where it is helpful to look at Ft/Vce and Ft contour graphs. First look at the power limits and then at the Beta/Ic curve, and determine what your limits are for power and linear range. Then look at the contour or Ft graph to see how high you can go within those bounds.
Another consideration that begets watching Cj values is reactance. If your device is spec'd at high Ft but has gobs of Cob, it might cause stability problems for the rest of the circuit. In my opinion, lower Cj is almost always better. If another part of the circuit oscillates when a faster part is installed, I would tend to see if I can improve stability without needing to downgrade.
In all, my preference would be to try and approach the speed barrier. A limit to the speed of electrons through the junction implies, to me, something like a 2-way saturable current source, which means it will allow current to pass either way up to the limit. My reasoning is that a current source is not reactive, especially an atomic-scale current source. this implies more controlled behavior.
I have a follow up question that will come after any discussion on this.
Am I right?
- keantoken
That would be the speed of light.
Actually , the "speed limit" is the manufacturing and thickness of the base layer which determines the carrier lifetime. In particular, the thickness of the base must be much less than the diffusion length of the electrons. So , a thinner- smaller die will be faster by the physics within. The electrons are limited by the speed of light , but the base carriers .. and how many survive before recombining at the emitter , determine "speed". Of course , I don't care if one device has a higher Ft. I look for Cob,Ft,noise.. and at what level it will be used in my circuit . I'm evaluating the MPSA18 vs. my favorite ksc1845 in this way to replace my input pairs.
OS
OS
MPSA18 can be a real P.I.T.A. to match !
They work very nicely in the CM area too.
Funny things can sometimes happen too, when testing for HFE if you place another one against it, like you would for bonding together.
Alex
I guess I'll buy 50 for Xmas.
Ft and Cob are two different parameters, and they shouldn't be compared. And they both have their usefulness.
The capacitance has no first order influence on Ft, because Ft relates to currents.
And transistors can indeed have a pretty high Ft with substantial capacitances.
This was the case with early "fast" transistors, which required heavy neutralization to operate properly.
The capacitance has no first order influence on Ft, because Ft relates to currents.
And transistors can indeed have a pretty high Ft with substantial capacitances.
This was the case with early "fast" transistors, which required heavy neutralization to operate properly.
The parameters I am most often interested in are the switching parameters, since I do a lot of switching design.
When switching parameters are available (and they often are not -- old transistors, with loose specs, like 2N2222 and MJ350, are poorly specified), they usually go something like 2N4401: t_r, t_d, t_f all around 50ns, t_stg around 200ns! This suggests it isn't useful above ~2.5MHz, because you would then spend all the on-time sucking base charge out of the thing, after charging it up with a huge turn-on pulse. But I've used 2N4403 as high as 35MHz! A closer look reveals hFE (at whatever Vce) is fairly high at the test current, but the hFE used in the saturation test is 10. So they're oversaturating it, which gives a lower Vce(sat) figure, but pumps excessive charge carriers into the base, slowing it down.
Higher gain transistors have this, much more dramatically. ZTX651 for instance is rated for 2A Ic, and has hFE > 100 up to 1A, yet they show the switching data at hFE = 10. It should be no surprise that the storage time is a whopping 900ns! This transistor is almost like a MOSFET in drive requirements; if you drive it accordingly, accepting a somewhat smaller operating range (lower Ic / higher Vce(sat)), you'll get plenty of speed out of it.
One exception I've seen is KTC5001, which is rated for something like 30V, 8A and hFE > 80 up to that point. Saturation is actually given at hFE = 80, and despite the very high gain, storage time is still reasonable.
The implication of this, applied to analog circuits is, saturation recovery of course, and, if you drive it harder, you can make it go faster, but only to a point.
Actually, the electrons are limited by either avalanche or thermal drift velocity.
Avalanche velocity isn't a parameter I've seen specified or derived, but it could be calculated from electric field profile, either a uniform electric field inside intrinsic silicon (not a very useful material outside of the physics lab), or the approximately triangular field inside a PN junction. Or calculated from the avalanche energy, which I suppose ought to be the band gap. In that case, it would be v_e = sqrt(2 Eg / m*), where m* is the effective mass (which is not the free electron mass, because electrons do different things when they get stuck inside crystals!).
Thermal velocity is easy to calculate, and it's around 10^5 m/s for silicon at room temperature. This is the same idea as the speed of sound, in air, at STP. Things can travel faster than this velocity, but the characteristics are different: ballistic instead of thermal drift, subsonic vs. supersonic. In either case, you can expect different behavior around that limit.
Down in the thermal regime, electric field is proportional to velocity (this is just Ohm's law!). If avalanche occurs before thermal velocity is reached, you'd never even be able to test "superthermal" velocity, at least in that material.
The result for transistors is, charge moves s-l-o-w-l-y across it. For weaker fields, like the field across a conductive chunk of doped silicon, it could take a long time indeed to neutralize the charge, even though the width is fractional micrometers. There isn't anything you can do about that, because you can only increase base current so much, in an effort to move that current, before either 1. you reach diminishing returns (which is fT), or 2. you reach the physical barrier and you literally cannot drag any more charge out of the poor thing!
Notice that electron drift velocities for silicon are on the order of 10^3 m/s. Vacuum tubes are ballistic transport, so they don't have a single velocity, but the average will be some fraction of the plate voltage, i.e., whatever velocity electrons have at maybe 100eV kinetic energy, which might be in the 10^6 m/s range. Vacuum tubes have proportionally larger dimensions (mm vs. um distances), so they are useful to roughly the same frequency ranges (i.e., tens of MHz, give or take an order of magnitude).
Tim
When switching parameters are available (and they often are not -- old transistors, with loose specs, like 2N2222 and MJ350, are poorly specified), they usually go something like 2N4401: t_r, t_d, t_f all around 50ns, t_stg around 200ns! This suggests it isn't useful above ~2.5MHz, because you would then spend all the on-time sucking base charge out of the thing, after charging it up with a huge turn-on pulse. But I've used 2N4403 as high as 35MHz! A closer look reveals hFE (at whatever Vce) is fairly high at the test current, but the hFE used in the saturation test is 10. So they're oversaturating it, which gives a lower Vce(sat) figure, but pumps excessive charge carriers into the base, slowing it down.
Higher gain transistors have this, much more dramatically. ZTX651 for instance is rated for 2A Ic, and has hFE > 100 up to 1A, yet they show the switching data at hFE = 10. It should be no surprise that the storage time is a whopping 900ns! This transistor is almost like a MOSFET in drive requirements; if you drive it accordingly, accepting a somewhat smaller operating range (lower Ic / higher Vce(sat)), you'll get plenty of speed out of it.
One exception I've seen is KTC5001, which is rated for something like 30V, 8A and hFE > 80 up to that point. Saturation is actually given at hFE = 80, and despite the very high gain, storage time is still reasonable.
The implication of this, applied to analog circuits is, saturation recovery of course, and, if you drive it harder, you can make it go faster, but only to a point.
That would be the speed of light.
Actually, the electrons are limited by either avalanche or thermal drift velocity.
Avalanche velocity isn't a parameter I've seen specified or derived, but it could be calculated from electric field profile, either a uniform electric field inside intrinsic silicon (not a very useful material outside of the physics lab), or the approximately triangular field inside a PN junction. Or calculated from the avalanche energy, which I suppose ought to be the band gap. In that case, it would be v_e = sqrt(2 Eg / m*), where m* is the effective mass (which is not the free electron mass, because electrons do different things when they get stuck inside crystals!).
Thermal velocity is easy to calculate, and it's around 10^5 m/s for silicon at room temperature. This is the same idea as the speed of sound, in air, at STP. Things can travel faster than this velocity, but the characteristics are different: ballistic instead of thermal drift, subsonic vs. supersonic. In either case, you can expect different behavior around that limit.
Down in the thermal regime, electric field is proportional to velocity (this is just Ohm's law!). If avalanche occurs before thermal velocity is reached, you'd never even be able to test "superthermal" velocity, at least in that material.
The result for transistors is, charge moves s-l-o-w-l-y across it. For weaker fields, like the field across a conductive chunk of doped silicon, it could take a long time indeed to neutralize the charge, even though the width is fractional micrometers. There isn't anything you can do about that, because you can only increase base current so much, in an effort to move that current, before either 1. you reach diminishing returns (which is fT), or 2. you reach the physical barrier and you literally cannot drag any more charge out of the poor thing!
Notice that electron drift velocities for silicon are on the order of 10^3 m/s. Vacuum tubes are ballistic transport, so they don't have a single velocity, but the average will be some fraction of the plate voltage, i.e., whatever velocity electrons have at maybe 100eV kinetic energy, which might be in the 10^6 m/s range. Vacuum tubes have proportionally larger dimensions (mm vs. um distances), so they are useful to roughly the same frequency ranges (i.e., tens of MHz, give or take an order of magnitude).
Tim
Keantoken,
An understanding of the SPICE BJT model and the hybrid pi model is all you need to evaluate different transistors and their parameters. The SPICE parameters related to device speed are Cjeo, Cjco, and Tf. (Tr relates to storage time for a saturated switch, but has no effect on a transistor biased in the active region.) When you run an LTspice .op simulation the error log will have a report of the transistor operating point. The report lists Cbe, Cbc, and fT. There parameters are related by the equations below:
fT=1.0/(2*pi*(Cbc+Cbe))
Cbe=Cje+Tf*gm
Cbc=Cjc
Cje is Cjeo adjusted for the operating point
Cjc is Cjco adjusted for the operating point
See wkwmodels.pdf for a little more information.
One problem with the SPICE model is that Tf (fT) variations with Ic are not accurately accounted for. (I know you have looked at many data sheets and are well aware of the fact that fT varies with Ic.) In other words, the SPICE model is really valid at only a specific operating point, or at best, over a small range of operating points.
fT in itself is not a real useful parameter, but it is useful in making a relative evaluation of different devices, recognizing that it varies with Ic. BTW, a knowledge if Ciss and Crss is not sufficient, because of the Tf*gm term above. This term is often the dominate term. Note also that gm=38.3*Ic.
Rick
An understanding of the SPICE BJT model and the hybrid pi model is all you need to evaluate different transistors and their parameters. The SPICE parameters related to device speed are Cjeo, Cjco, and Tf. (Tr relates to storage time for a saturated switch, but has no effect on a transistor biased in the active region.) When you run an LTspice .op simulation the error log will have a report of the transistor operating point. The report lists Cbe, Cbc, and fT. There parameters are related by the equations below:
fT=1.0/(2*pi*(Cbc+Cbe))
Cbe=Cje+Tf*gm
Cbc=Cjc
Cje is Cjeo adjusted for the operating point
Cjc is Cjco adjusted for the operating point
See wkwmodels.pdf for a little more information.
One problem with the SPICE model is that Tf (fT) variations with Ic are not accurately accounted for. (I know you have looked at many data sheets and are well aware of the fact that fT varies with Ic.) In other words, the SPICE model is really valid at only a specific operating point, or at best, over a small range of operating points.
fT in itself is not a real useful parameter, but it is useful in making a relative evaluation of different devices, recognizing that it varies with Ic. BTW, a knowledge if Ciss and Crss is not sufficient, because of the Tf*gm term above. This term is often the dominate term. Note also that gm=38.3*Ic.
Rick
Okay then, lots of helpful information.
So there are two groups of interacting parameters. The first is the set of capacitances, and the second is the Tf*Gm term.
Is it possible to create a hybrid or product of these and create a general parameter that sums them both up?
For instance, say we take 1/Cob=bjork. Higher bjork is then a good thing. Let's make Ft*gm=F. Higher F is also a good thing.
Then lets try
F*bjork=performance
If Bjork is very low but F is high, performance will still be average or mediocre.
Same for if Bjork is high but F is very low.
The performance factor could be tailored for the application, by inserting the source impedance and quiescent current:
(1/(Zin*<some mix of C parameters>)*(Tf*Gm)
With a real method of choosing transistors for a task, it would become more than guesswork for amp designers.
- keantoken
So there are two groups of interacting parameters. The first is the set of capacitances, and the second is the Tf*Gm term.
Is it possible to create a hybrid or product of these and create a general parameter that sums them both up?
For instance, say we take 1/Cob=bjork. Higher bjork is then a good thing. Let's make Ft*gm=F. Higher F is also a good thing.
Then lets try
F*bjork=performance
If Bjork is very low but F is high, performance will still be average or mediocre.
Same for if Bjork is high but F is very low.
The performance factor could be tailored for the application, by inserting the source impedance and quiescent current:
(1/(Zin*<some mix of C parameters>)*(Tf*Gm)
With a real method of choosing transistors for a task, it would become more than guesswork for amp designers.
- keantoken
keantoken,
I goofed in my last post. I should have written:
fT=gm/(2*pi*(Cbc+Cbe)) ... I forgot to include the gm term.
So the complete expression for fT is:
fT=gm/(2*pi*(Cjc+Cje+Tf*gm))
LTspice will compute fT, gm, Cbc and Cbe based on the model parameters Cjco, Cjeo, and Tf and the operating point which gives Ic (gm=38.3*Ic). The error log will show these values, if you do an .op analysis. Of course, you could do the calculations yourself.
As I said, Tf usually dominates the frequency response, but Cjc and Cje also contribute.
Sorry about the mistake.
Rick
I goofed in my last post. I should have written:
fT=gm/(2*pi*(Cbc+Cbe)) ... I forgot to include the gm term.
So the complete expression for fT is:
fT=gm/(2*pi*(Cjc+Cje+Tf*gm))
LTspice will compute fT, gm, Cbc and Cbe based on the model parameters Cjco, Cjeo, and Tf and the operating point which gives Ic (gm=38.3*Ic). The error log will show these values, if you do an .op analysis. Of course, you could do the calculations yourself.
As I said, Tf usually dominates the frequency response, but Cjc and Cje also contribute.
Sorry about the mistake.
Rick
Keantoken,
gm is given by 38.7*Ic at room temperature; Ic is the DC operating point. This is a fundamental property of BJTs and gm is the same for all transistors.
I don't know much about semiconductor physics, but Tf is related to the charges of carriers in the base region, and I don't think thermal drift or avalanche velocity have anything to do with it.
Rick
gm is given by 38.7*Ic at room temperature; Ic is the DC operating point. This is a fundamental property of BJTs and gm is the same for all transistors.
I don't know much about semiconductor physics, but Tf is related to the charges of carriers in the base region, and I don't think thermal drift or avalanche velocity have anything to do with it.
Rick
Fairchild vs. NXP BC550
The Fairchild BC550 has an Ft of 300MHz, whereas the NXP version has 100MHz Ft.
I the Fairchild has 3.5p Cob and 9p Ceb. The NXP version has 1.5p Cc and 11p Cib.
This gives someone a lot to think about concerning the interaction between C parameters and speed.
Capacitors can actually act like voltage dividers. Put a 1uF cap on top of a 9uF one and you have a divider of 10. Looking at it this way, we see that when biased, a transistor's effective Cob will be higher if the transistor has low Ceb, because Ceb reduces Miller feedback. And this brought me to the question: Which is better, high Cob/low Ceb or low Cob/high Ceb?
- keantoken
The Fairchild BC550 has an Ft of 300MHz, whereas the NXP version has 100MHz Ft.
I the Fairchild has 3.5p Cob and 9p Ceb. The NXP version has 1.5p Cc and 11p Cib.
This gives someone a lot to think about concerning the interaction between C parameters and speed.
Capacitors can actually act like voltage dividers. Put a 1uF cap on top of a 9uF one and you have a divider of 10. Looking at it this way, we see that when biased, a transistor's effective Cob will be higher if the transistor has low Ceb, because Ceb reduces Miller feedback. And this brought me to the question: Which is better, high Cob/low Ceb or low Cob/high Ceb?
- keantoken
Keantoken,
The differences between the Fairchild and NXP data sheet do seem a little strange. However, the ft or the Fairchild part is a typical value and for NXP it is a minimum. There can be a large variation of parameters for BJTs and this may be why the large difference. The Cc value for the NXP part seems too low.
The best way to answer your question is to do an analysis using the hybrid pi model. Assume we have a common emitter amplifier driven be a source with a resistance of Rs, an emitter resistor Re and a collector resistor Rc. For this circuit the low frequency voltage gain is Av=-Beta*Rc/(Rs +Ri). The 3 db frequency is given by
f3db=(Rs+Ri)/(2*pi*C*rbe*(Rs+Re))
where rbe=beta/gm
Ri=rbe+Re*(1+Beta)
C=Cbe+Cbc*(1+gm*(Re+Rc))
where Cbe and Cbc are defined in post 7. In the expression for C above, the last term Cbc*(1+gm*(Rc+Rc)) is the Miller capacitance. Obviously, you want C to be as small as possible, but you also want some voltage gain. This is the tradeoff and the gain bandwith product is given by
gm*Rc/(2*pi*C*(Rs+Re))
Rick
The differences between the Fairchild and NXP data sheet do seem a little strange. However, the ft or the Fairchild part is a typical value and for NXP it is a minimum. There can be a large variation of parameters for BJTs and this may be why the large difference. The Cc value for the NXP part seems too low.
The best way to answer your question is to do an analysis using the hybrid pi model. Assume we have a common emitter amplifier driven be a source with a resistance of Rs, an emitter resistor Re and a collector resistor Rc. For this circuit the low frequency voltage gain is Av=-Beta*Rc/(Rs +Ri). The 3 db frequency is given by
f3db=(Rs+Ri)/(2*pi*C*rbe*(Rs+Re))
where rbe=beta/gm
Ri=rbe+Re*(1+Beta)
C=Cbe+Cbc*(1+gm*(Re+Rc))
where Cbe and Cbc are defined in post 7. In the expression for C above, the last term Cbc*(1+gm*(Rc+Rc)) is the Miller capacitance. Obviously, you want C to be as small as possible, but you also want some voltage gain. This is the tradeoff and the gain bandwith product is given by
gm*Rc/(2*pi*C*(Rs+Re))
Rick
Datasheets looking strange seems the norm for rationalised product lines.
Fairchild's data sheet (rev2 2002) lumps BC550 with BC547,8,9, assigning them largely identical specs and curves excepting Vcebo and Hfe ranges. Noise figures scarcely differ. What's more, it appears that the same set of curves are used on the PNP devices. This is not a good sign.
I get the impression that these are not correct datasheets or the parts are just not to Philips (NXP) original specs. ON Semi's (rev.2 2007) datasheet seems to be another range again.
I would be wary about the correlation of models/manufacturers with these or any multi-source parts that seem to have "evolved" in recent years.
Fairchild's data sheet (rev2 2002) lumps BC550 with BC547,8,9, assigning them largely identical specs and curves excepting Vcebo and Hfe ranges. Noise figures scarcely differ. What's more, it appears that the same set of curves are used on the PNP devices. This is not a good sign.
I get the impression that these are not correct datasheets or the parts are just not to Philips (NXP) original specs. ON Semi's (rev.2 2007) datasheet seems to be another range again.
I would be wary about the correlation of models/manufacturers with these or any multi-source parts that seem to have "evolved" in recent years.
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