The DAC's clock generator circuit sets an absolute floor for the DAC's final net clock jitter. This is true for both SPDIF and USB. Most of the net jitter resulting from an SPDIF connected system (where, the transport is the data flow control master) comes from jitter already on the SPDIF link signal that has not been suppressed by the DAC's input receiver PLL, or by an subsequent ASRC circuit. A properly implemented Async. USB has the potential for a lower net system jitter than does SPDIF, because it makes the DAC the data flow control master.
So is using say an iPurifier3 by iFi audio | USB Audio and Data Signal Filter in a ESS chip DAC like Topping D50s beneficial to reduce USB signal jitter and hence, for better sound quality?
It's at least hard to believe. And as the manfacturer does not actually say what it really does it's also hard to speculate about it. Tried to find pictures of the inside but could not find detailed enough pictures to be able to tell whats going on inside.
Btw. reclocking the USB signal itself is kind of bogus and of little to no help for the jitter specs of the i2s output signals of a USB>I2S bridge, at least for USB async transfer that is.
Btw. reclocking the USB signal itself is kind of bogus and of little to no help for the jitter specs of the i2s output signals of a USB>I2S bridge, at least for USB async transfer that is.
Lots of mysticism here about jitter.
Very recreational to read.
The ESS DAC's datasheets are secret. From were you have these information's? Did you buy ESS DAC's and therefore sign the agreement not to make public the data?
Very recreational to read.
The ESS DAC's datasheets are secret. From were you have these information's? Did you buy ESS DAC's and therefore sign the agreement not to make public the data?
Last edited:
For many ESS chips datasheets are free now.
Yes, I had signed NDA with ESS and have an access to some non public documents.
But, as I said, some datasheets are now (at least 3-4 month) available for all, for example - ES9038Pro/Q2M
How's how I see it, and Texas DIR9001 is PPL suppressing the SPDIF jitter to 50ps, which is low. I read non sync Dac's are in the region of 1-2ns. I've read about 200ps for some Async USB DAC's but not proven by measurements, whereas Texas's figures are completely trustworthy.
Usually if a manufacturer decides not to publicise its figures it's because the figures are not conducive to sales and best left to speculation.
It is low just if to compare with an ancient CS8412/etc (200ps) and not to use higher than CD-DA (44/16) formats.
Otherwise - why many people use various jitter reduction methods (with different efficiency - simple re-clock, ASRC, FIFO, etc.) to reduce the receiver and also the source jitter?
Not only do manufacturers have to publish the specifications, the user must understand them. Plus, understand the operation of the circuits to which they refer. The DIR9001 has two clock modes, one is based on a PLL, and the other is based on a free running oscillator. One of those modes is utilized under certain signal conditions, while the other is switched in under different signal conditions. I'll leave it to you to figure out what the respective conditions are. Suffice to say, the result is not simply a fixed 50ps. recovered clock jitter no matter the signal condition. I'll just leave it at that.
Texas say the crystal is only needed when the SPDIF is non operational and downstream components need the consistent clock. It's not used for the PLL so the ~50ps figure is the only condition.
...its a typical, non-guaranteed RMS value, measured as 'period' jitter. Probably they measure it with a fancy scope that can measure period and or interval jitter, aka 'far-out phase noise.' That type of phase noise tends to affect the noise floor more than the sound. OTOH 'close-in' phase noise can have more effect on sound, but it harder to measure and requires special equipment.
The other thing is not to confuse J-Test measurements used at some audio websites as being a fully valid way to measure jitter. Its for measuring deterministic jitter, such as can occur with SPDIF. Random jitter is often assumed to be much less audible, but when its close-in phase noise that isn't necessarily the case.
Regarding async USB, it can easily best SPDIF in both far-out and close-in phase noise, as others have already tried to explain. Phase noise from the best dac clocks can be measured as being in the low femtosecond range. However, that's not being measured as RMS period jitter beyond 12kHz offset from the carrier (a common type of scope-based jitter measurement).
If it is desired to reduce SPDIF jitter to that of async USB, its possible to do using a crystal-clocked FIFO buffer. There are a few people that make such devices for diy dac use
IME J-Test is a valid measurement of SPDIF implementation. It is not about measuring jitter.
Another thing is that MCK seems to be the most problematic for SPDIF receivers. Here is AK4118 I2S output of 24-bit J-Test without MCK:
Another view of the same:
So not bad at all and may work nicely with DACs that don't require MCK.
However when MCK is used things look much worse (here AK4118 to AK4490):
That is typical of AK4118 without SRC (as in Topping D90).
IMO the easiest way to get clean SPDIF output is with SRC (as in ES9038 or with AK4137).
Another thing is that MCK seems to be the most problematic for SPDIF receivers. Here is AK4118 I2S output of 24-bit J-Test without MCK:
Another view of the same:
So not bad at all and may work nicely with DACs that don't require MCK.
However when MCK is used things look much worse (here AK4118 to AK4490):
That is typical of AK4118 without SRC (as in Topping D90).
IMO the easiest way to get clean SPDIF output is with SRC (as in ES9038 or with AK4137).