The fact that you and your customers don’t like the AN DAC3 in no way invalidates my statement that Audio Note DACs are highly regarded. (I don’t like the DAC3, either.) AN has many happy customers and many rave reviews in the mainstream and not-so-mainstream audio press. I haven’t seen any rave reviews of your DAC in any audio press.
Have you ever looked at the output of a DAC? It’s a stair-stepped ANALOG of the digital input. If there is jitter in the timing of those stair-steps then there is jitter in the analog output of the DAC. You claim to be able to hear 1ps of jitter. If the jitter didn’t cross the boundary that separates the digital and analog domains and appear in the analog output of the DAC, how can you hear it?
Look at the data sheet of most any multi-bit, audio DAC and you will see a spec for settling time. That’s the time it takes for the analog output to reach the level that represents the ANALOG of the digital input. The TDA1541, Thorsten’s favorite, settles to within +/- 1 LSB in 1 MICROsecond. Although the Philips spec doesn’t give the range settled, the norm for settling time is a one-half of a full-range current swing. The settling time varies depending on the numeric distance between consecutive samples and, in some cases, the number of bits changing. A smaller current swing will settle in less time. If two successive samples are identical, the settling time is zero.
Fact: The TDA1541 typically takes up to one MICROsecond, or longer, for the correct current to appear at the output of the DAC.
Fact: The actual settling time depends on the data.
Conclusion: It looks like data induced jitter to me.
Good question, but I didn't say DACs had microseconds of jitter; I said the jitter was MEASURED in MICROseconds, as the Philips spec proves.
jbokelman said:
Err,
Isnt this just a microsec of DELAY (BCK change to analog output change) which is not always exactly 1.0000... microsec but a bit more/less. That would then be the jitter which comes from:
- DELAY not being equal for all data/steps between samples
internally in the DAC = jitter
- BCK jitter.
Can't imagine one can hear changes to the clock jitter (induced with BCK) if the delay would range from 0 to microseconds depending on the data. But if there is an average delay of one microsecond, jitter would not be in microseconds.
The BCK jitter is what can be minimized by working on the clocks.
Writing this without looking at the spec or having ever done any jitter measurements (with what ?? 😀 ).
The other
jbokelman said:
The DAC output is the result of both data and clock.
The settling time should not be confused with jitter.
Assumed that the data is correct, the analog signal distortion due to the DAC depends on conversion timing errors as the timing error is converted in an amplitude error.
It can easilly be meaured, I did that feeding known jitter to a PCM63 (using a VCXO). Sidebands appear, depending on amplitude and frequency of jitter added (the PCM63 is more jitter sensitive for higher audio frequencies).
I never said my customers didn't like their AN-DAC3, but they all seem to prefer either our own DAC or the DAC clock upgrade I offer.
Our DAC is never reviewed as it is a DIY DAC hence a direct thread to the advertisement income of any audio magazine.
cheers
Of course you don’t hear the effects of settling time because it is omnipresent. You would probably recognize it once it’s gone.
Settle time illustration
Pictured is a highly stylized representation of the effects of settling time. The dotted lines show the output of an ideal DAC. Samples 1 and 6 are both zero. Samples 2 and 5 are same and are a little higher than zero. Samples 3 and 4 are the same and are a lot higher than zero.
The solid lines show the output of a real DAC. The pairs of samples that should be identical are not. They differ in the time to reach the correct height, the average height during the sample period, and the area under the curve for each sample period.
I called the aberrations caused by settling time “intrinsic jitter” because jitter seems to be the only digital aberration discussed in this forum. Also, the effects of settling time are similar to jitter. Jitter, as you all know it, changes the time a sample starts and stops and that changes the area under the curve and the amount of work/energy that sample imparts to the resulting output signal. As you can clearly see, the effects of settling time also affects the area under the curve. And like some forms of jitter, settling time aberrations are related to the data.
In the old days of parallel DACs, S/H registers were commonplace. Because the DACs were expensive and required numerous latches and support logic, the left/right channel data was decoded by a single DAC and the left/right channel output was separated by S/H registers. The use of S/H also eliminated the effects of settling time and all upstream clock jitter. In fact, recommended S/H delay times were part of the DAC chip specs.
As DACs got faster, settling time became less of an issue and the pressure to reduce costs led to the serial interface, stereo DACs, upsampling, etc. and the S/H was eliminated. With the renaissance of non-oversampling and the rediscovery of ancient DAC chips, like the TDA1541, I am surprised no one has resurrected the venerable S/H.
Settle time illustration
Pictured is a highly stylized representation of the effects of settling time. The dotted lines show the output of an ideal DAC. Samples 1 and 6 are both zero. Samples 2 and 5 are same and are a little higher than zero. Samples 3 and 4 are the same and are a lot higher than zero.
The solid lines show the output of a real DAC. The pairs of samples that should be identical are not. They differ in the time to reach the correct height, the average height during the sample period, and the area under the curve for each sample period.
I called the aberrations caused by settling time “intrinsic jitter” because jitter seems to be the only digital aberration discussed in this forum. Also, the effects of settling time are similar to jitter. Jitter, as you all know it, changes the time a sample starts and stops and that changes the area under the curve and the amount of work/energy that sample imparts to the resulting output signal. As you can clearly see, the effects of settling time also affects the area under the curve. And like some forms of jitter, settling time aberrations are related to the data.
In the old days of parallel DACs, S/H registers were commonplace. Because the DACs were expensive and required numerous latches and support logic, the left/right channel data was decoded by a single DAC and the left/right channel output was separated by S/H registers. The use of S/H also eliminated the effects of settling time and all upstream clock jitter. In fact, recommended S/H delay times were part of the DAC chip specs.
As DACs got faster, settling time became less of an issue and the pressure to reduce costs led to the serial interface, stereo DACs, upsampling, etc. and the S/H was eliminated. With the renaissance of non-oversampling and the rediscovery of ancient DAC chips, like the TDA1541, I am surprised no one has resurrected the venerable S/H.
The settling time of a DAC can be split into two types: linear settling and non-linear settling. Linear settling is primarily determined by RC time constants inside the DAC chip and/or the time constant of an external I/V converter. It is exactly equivalent to lowpass filtering the DAC output, typically at a fairly high cutoff frequency (time constant << DAC sample rate). As long as the time constant is short enough linear settling does not degrade the DAC output and is in no way equivalent to jitter.
Nonlinear settling is most commonly caused by slew rate limitations in the I/V converter. Proper design of the I/v converter WRT large-signal bandwidth and output swing can minimize the effects of slew rate. A well designed DAC will have negligible nonlinear distortion.
There is a possible signal-dependent jitter source inside the DAC chip and that is internal clock skew on the sample clock. Typically the sample clock needs to be gated and routed to a number of analog switches (transmission gates) which have some physical separation on the chip; if the clock does not arrive at precisely the same time this can cause a jitter-like effect. The effect is highly dependent on the DAC topology. In any case, careful physical design (layout) of the DAC chip can bring the clock skew down to the picosecond level (or better).
Nonlinear settling is most commonly caused by slew rate limitations in the I/V converter. Proper design of the I/v converter WRT large-signal bandwidth and output swing can minimize the effects of slew rate. A well designed DAC will have negligible nonlinear distortion.
There is a possible signal-dependent jitter source inside the DAC chip and that is internal clock skew on the sample clock. Typically the sample clock needs to be gated and routed to a number of analog switches (transmission gates) which have some physical separation on the chip; if the clock does not arrive at precisely the same time this can cause a jitter-like effect. The effect is highly dependent on the DAC topology. In any case, careful physical design (layout) of the DAC chip can bring the clock skew down to the picosecond level (or better).
jbokelman
Your statements here regarding Sample & Holds are completely humorous. First, the current generations of DAC’s have deglitching circuitry! That means a S&H is not required or even remotely needed. So, If we add a sample hold it would have to be a discrete one cause the monolithic ones or horrible. That means adding bunch of parts. So now, for no reason at all we have had to add new timing hardware, match fets, resistors opamps, low DA and Leakage caps to re-quanatize something that already been done, not to funny. So would you make these recommendations in design reviews?
As far as Bi Phase Mark goes would you even know how to decode or encode it from NRZ data stream, I bet not. My self, I did my first Bi Phase Mark decoder and encoded at TI back in 1981, whoopee.
So it seems you enjoy your habit here of arguing over issues that you just don’t completely grasp. Maybe, if you take the time to listen to Guido, Jocko or others you might be able to improve your technical skill in this engineering area.
Back to jitter, while we do have some intrinsic jitter in all digital systems the major source of jitter in the audio CD DAC chain is cause by a number poorly implemented design issues. System noise, grounding methods, power supplies, master clocks, logic types, impedance mismatches – reflections and more.
Your statements here regarding Sample & Holds are completely humorous. First, the current generations of DAC’s have deglitching circuitry! That means a S&H is not required or even remotely needed. So, If we add a sample hold it would have to be a discrete one cause the monolithic ones or horrible. That means adding bunch of parts. So now, for no reason at all we have had to add new timing hardware, match fets, resistors opamps, low DA and Leakage caps to re-quanatize something that already been done, not to funny. So would you make these recommendations in design reviews?
As far as Bi Phase Mark goes would you even know how to decode or encode it from NRZ data stream, I bet not. My self, I did my first Bi Phase Mark decoder and encoded at TI back in 1981, whoopee.
So it seems you enjoy your habit here of arguing over issues that you just don’t completely grasp. Maybe, if you take the time to listen to Guido, Jocko or others you might be able to improve your technical skill in this engineering area.
Back to jitter, while we do have some intrinsic jitter in all digital systems the major source of jitter in the audio CD DAC chain is cause by a number poorly implemented design issues. System noise, grounding methods, power supplies, master clocks, logic types, impedance mismatches – reflections and more.
The thing is, most of the DAC projects around here are not using current generation chips. The favored chips are close to 20 years old and they don't have deglitching circuits built in. If they did, the datasheets wouldn't specify 1us typical settling times. Maybe you missed that part of the discussion.
You’re damn right, I would, and I’ve had many heated discussions with EE’s trying to get them to “think outside the box,” as they say. But this is not the time or place for me to list all my engineering accomplishments in both software and hardware.
Whoopee, indeed. You must be one of them EE-types. I’ve worked with a number of EE’s through the years. They’re real smart but they have no imagination. Their world-view is limited to what they learned in school.
I thought the switch to CMOS years ago was, in large part, to reduce power consumption. But what do I know. I’m just a dumb programmer. Yeah, I’m real dumb. That’s how come I was able to retire at very young age while all you real smart, college educated, EE-types are still working.
So you're retired......
BFD.
I guess that makes you smarter and richer than Bill Gates and/or Ross Perot.
Like any of us care, or are impressed.
No imagination?????? Speak for yourself, not us.
But I must be smart, since I never learned squat in school.
Except how to **** off all the professors.
Jocko
BFD.
I guess that makes you smarter and richer than Bill Gates and/or Ross Perot.
Like any of us care, or are impressed.
No imagination?????? Speak for yourself, not us.
But I must be smart, since I never learned squat in school.
Except how to **** off all the professors.
Jocko
jewilson said:
Good suggestion. I spent some time pouring over the archives to see what I could learn from Jocko and Guido. Jocko’s expertise appears to be in RF, not digital. When Bernard wanted to know which 74 logic family to use for >100MHz and Jocko recommended ECL. Is ECL a 74 logic family?
Jocko Homo said:
Is ECL within the capabilities of the average Joe?
Guido’s expertise seems to be in layout, grounding, and related items. He really likes serial resistors and he uses some unorthodox symbols in his schematics. For example, he uses the symbol for an AND gate to represent a NOR gate. I don’t know, maybe they use different symbols in Europe. The way he organizes the clocks in his DAC violates every rule of proper clock generation and distribution I learned when I worked for a mainframe company.
Ha, ha, ha!
That is because it was a mainframe company, not the inside of a CD player or DAC.
But you are correct. RF is my background.
You can build your own ECL for our purposes with 2 transistors, 3 resistors, and a bias network. How hard can that be??
As for S/H circuits...........
They were commonplace at one time (YUK!), and the DAC chip makers learned how to make decent ones that did not need de-glicthers. In the meantime.........it gave rise to companies like UltraAnalog, who's main selling point was that they invented a special de-glitcher.
One that allowed them to use crap like 5532s in the I/V stage.
(You can't prove that by looking inside one.........they remove all the ID markings. But if you want one, I have 2 to sell. Cheap.)
Speaking of I/Vs......and no imagination.........I wonder who can name the goofball who was one of the first......if not the first......to use a true transimpedance amp for an I/V????
Anyone????
Hint: It was back in '89............
I don't need no steenking boxes............
Jocko
Only semi-retired
That is because it was a mainframe company, not the inside of a CD player or DAC.
But you are correct. RF is my background.
You can build your own ECL for our purposes with 2 transistors, 3 resistors, and a bias network. How hard can that be??
As for S/H circuits...........
They were commonplace at one time (YUK!), and the DAC chip makers learned how to make decent ones that did not need de-glicthers. In the meantime.........it gave rise to companies like UltraAnalog, who's main selling point was that they invented a special de-glitcher.
One that allowed them to use crap like 5532s in the I/V stage.
(You can't prove that by looking inside one.........they remove all the ID markings. But if you want one, I have 2 to sell. Cheap.)
Speaking of I/Vs......and no imagination.........I wonder who can name the goofball who was one of the first......if not the first......to use a true transimpedance amp for an I/V????
Anyone????
Hint: It was back in '89............
I don't need no steenking boxes............
Jocko
Only semi-retired
The facts or Bud at high speeds HCMOS will uses more power that ALS, check out the clock speed vs. power. But that not the real issue, I was discussing noise cause by some logic families when they undershoot ground and how that can effect other things like jitter.
Well it good to know that some one has taken up the cause to be the DIY biographer and has proclaimed him self Grand OZ..
😱
jbokelman said:
I have an analog background.
Among that I design pick up units for high speed optical recording (so far 16X DVD, but blu is cooking in our kitchen)
The essentials of AD and DA are in the conversion. That's an area where analog, RF, EMC and layout are quite welcome.
I am not an expert in digital, maybe that is why I mix up symbols.
My clocking scheme may differ from what mainstream industry does, but that probably tells more about that industry than about myself.
best regards
Reading this prompted me to try a pair of 10nF 1206 NPO coupling caps on my nonOS dac.
With a 1206 resistor they make a very neat and compact package. They don't sound worse inferior than the Wima polyprops and Welwyn RC55 they replaced, perhaps a bit sharper but nothing that I imagine would cause trouble in a balanced sounding system.
With a 1206 resistor they make a very neat and compact package. They don't sound worse inferior than the Wima polyprops and Welwyn RC55 they replaced, perhaps a bit sharper but nothing that I imagine would cause trouble in a balanced sounding system.
Inspired by this thread I did some cap swapping too. I tried several ceramic and plastic caps. I even tried bypassing with silver mica caps.
All film caps sounded veiled, including vishay KP1830. The ceramic caps I tried were notably better. The best result gave some Kermet NPO cap from mouser. I don't remember the actual type.
Bypassing didn't make an audible difference in any case.
All in all a very worthwhile upgrade.
All film caps sounded veiled, including vishay KP1830. The ceramic caps I tried were notably better. The best result gave some Kermet NPO cap from mouser. I don't remember the actual type.
Bypassing didn't make an audible difference in any case.
All in all a very worthwhile upgrade.
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