OK then moving on from that helpful feedback, is there anything we can do to make life for the output stage easier, beyond pure classA (with CCS loading to ensure constant draw)?
Improving the PSRR via totem poling output devices seems like one potential option, but I'm not completely sure this isn't practically equivalent to a discrete regulator on the supply. At the very least if the limitations are thermal and not due to beta-droop at high Ic then it could cut the number of paralleled devices required by sharing out the voltage drops. Maximum output will suffer due to the reduced swing though.
Improving the PSRR via totem poling output devices seems like one potential option, but I'm not completely sure this isn't practically equivalent to a discrete regulator on the supply. At the very least if the limitations are thermal and not due to beta-droop at high Ic then it could cut the number of paralleled devices required by sharing out the voltage drops. Maximum output will suffer due to the reduced swing though.
I just revisited the updated version and frankly, just for once, I am pleased with it. Just a few more things to work out, details to mop up, and it should be ready for a test run on the bench, live.
Then I put Wayne to hard labor. Before the trial boards are made, we will need to work out the technical details regarding the casing, sizes, distribution within the case, and so forth.
You up for that, Wayne?
Then I put Wayne to hard labor. Before the trial boards are made, we will need to work out the technical details regarding the casing, sizes, distribution within the case, and so forth.
You up for that, Wayne?
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I am aware of that process, however, I don't like it. And that blindly, I have never actually tried it, it's the idea I am not happy about. I like straight through designs, as few complications along the way as possible.
Besides, I'm not at all sure we'd save on the output stage, I think in the end we'd still have at least 8 pairs, 4 up and 4 down. So what do I gain?
4 pairs in totem pole rather than 8 paralleled output devices potentially improves the PSRR doesn't it? I rather suspect though you'd need more than 4 pairs in totem pole because with lower VCE, the beta droops faster.
I'm not claiming this is the best way to go, far from it. Rather just exploring possible avenues towards improving PSRR.
I'm not claiming this is the best way to go, far from it. Rather just exploring possible avenues towards improving PSRR.
But Rick, this also assumes we have a problem with PSRR. Yet, this may not be quite so.
First, do take another look at my initial essay - you will see a line of filter caps after the biggies, in a progressive descending order. Ending with a resistor and cap in series to the groung, which should rid me of suprious inductance from the big caps.
Second, I don't see the transformer as a problem at all, I understand Wayne has two whoppers which exceed his requirements by quite a marging. In such a case, they are not likely to become a source of any disturbance which could show up as a PSRR problem.
Regarding stacked transistors, off hand, I'd say I would need more like 6 pairs stacked, which is 24 output devices per channel. I haven't asked, but I suspect Wayne does not own any stock of Motorola/ON Semi. 😀 😀 😀
Very solid discussion, gentlemen, good to see. Yes, PSRR will be the big issue, and, it is about the OPS - if you separate out that section of the circuit and look at it, in sim with decent models, then it is susceptible to rail modulation, enough to cause real, audible problems.
The plaything I've got at the moment uses 8 pairs, currently, anything less means that you're fighting the weaknesses of real devices too much - I'm learning a lot at the moment!
Best let the Perreaux thing go, it was step on the journey, it did its job of getting me started, and allowing me to find out a lot about what matters ...
The plaything I've got at the moment uses 8 pairs, currently, anything less means that you're fighting the weaknesses of real devices too much - I'm learning a lot at the moment!
Best let the Perreaux thing go, it was step on the journey, it did its job of getting me started, and allowing me to find out a lot about what matters ...
I can vouch for the case ... 🙂
I dont see how adding more is going to be a PSRR issue, the PSU has to be done right to compensate , PSRR should not be an issue once we size the power supply, fully reg high voltage for VAS, 240kuf//ch..
Case, I got case baby , I GOT IT ...... 🙂
Looks good for VAS stage too .......
Beta Droop is a bigger concern than controlling PSRR ....
So you guys are building an actual amplifier? (Here I thought nothing productive was happening in this thread.)🙂
Cool. I normally don't care much for SS, but this is interesting, perhaps it would restore some interest in SS for me.
Cool. I normally don't care much for SS, but this is interesting, perhaps it would restore some interest in SS for me.
Its very simple - more devices in parallel means more parasitic capacitance to the rails aka Ccb.
Yes but 'a man should look for what is, not what should be' right? 🙄
That's not what i meant , the PSU has to be built to compensate , the Beta droop is of more concern, hence more outputs and 700yrs is along time between projects ......
🙄
What I'm suspecting Frank as a result of putting forward ideas on PSRR improvement right here on this thread is that PSRR really is an elephant in the room as regards amplifier SQ. I rather think there might be some kind of collective 'groupthink' at work here amongst amplifier designers to look the other way at PSRR issues. 'Problem, what problem - I have enough caps blah blah blah' 😀
Anyway I shall now shut up with my suggestions for PSRR improvements. Its been rather instructive 🙂
Everything secret degenerates ....🙄
I dont get you , put forward your discussion , no one is suggesting PSRR is not an issue , my position is that it pales vs beta droop , especially in your eg of 2 pr vs 8pr..
Sure - that fact has been noted hence my remark about changing your location...😛
Yes I agree,no-one is suggesting its not an issue but the vibe is its not so important an issue as its looking to me.
Yep beta droop is a major issue too, particularly into 1R.
Where did I suggest 2 pr? Never for driving 1R. Its been about whether 8 pairs is 'no worse' than 7 for PSRR. I've been maintaining that it must be but I've met all kinds of deflection and resistance 😀
Then show me , did you sim it? how much worse or how much better is 7 pr, I'm leaning towards 7 pr myself , D is suggesting 8 and is doing sims on both...
Tried simming PSRR quite some time ago and gave up because with the transistor models I had at the time (within LTSpice) the Ccb did not look to be correctly modelled. If anyone knows of models which do handle it correctly (i.e. non-linearly) then I'll be interested.
Good question Frank, probably my finger trouble combined with sheer laziness. To get those modelling features I'd need to set up a non-linear transient sim and thereby lose all the nice simplicity of the AC analysis (like straightfoward FR plots). It would also take a very long time to run - at least that's my expectation from running transient sims in the past.
Absolutely Rick! I believe a man should always prepare for the worst case he can think of. Generally, I am not a pessimist, where pessimist is an optimist with experience, but when you start dealing with something that contains around 200 parts per hannel, plus additional circuits, there are many ways to go wrong.
Ultimately, put it this way - Wayne and I could have done this on our own, via private correspondence, but we didn't, we want your feedback and ideas. There is BOUND to be something I either didn't think of, or someone has a better idea.
Regarding PSRR, how about adding more filter caps, say 1,000 uF or 2,200 uF, right next to each output device? Or perhaps settlo for 100 nF caps only?
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