Simplistic NJFET RIAA

Are you seeing that in a closed case? I found a slow steady climb in a closed case (with meter leads clipped in place and coming out of the case), but as soon as I opened the case to adjust the TP1-TP2 voltage would drop like a stone, then I had to wait maybe 30 minutes to see what effect my change made. I think that is the biggest challenge in high gain versions, especially for us obsessive types :)

Yes, I do see that fluctuations even when chassis is covered with lid. I made long wires connected to TPs.... However, I did not tighten the lid with screws, just placed it on top. Need to tight all screws and to see ....
 
I thought about installing high impedance voltage modules to the tp's but Salas thought it was a bad idea.
But maybe I will just for a while to see how the voltages fluctuates when ambient changes and to be able to better my enclosure...

Anyway, I haven't noticed that SQ should have changed when ambient has gone up or down...

Regards
 
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That's the K369's unfortunate trait with temperature when in small Rs LMC or MC app. Its own temperature rise alone is enough to drift its current draw. Large geometry high transconductance JFET you see. Largish capacitance and sensitive tempco goes with the low noise territory in such unipolar devices. In extreme case of varying ambient conditions it could be CCSed for R13 as I have shown you how in detail before. But better not introduce any additional current noise in the input stage by active sources if the thing is still not giving bad practical performance clues. At least when you will warm up the whole system for several minutes before listening. In MM and HMC config such an issue is almost irrelevant due to much higher Rs value (R2) which controls the K369 JFET bias better.
 
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It helps, that is why we use minisinks on the two K369s. But its not a differential amp so to have problems with THD when they drift bit differently. Their combined transconductance changes very little by their IDSS gains with temp. That is why you don't get sonic clues before the reading goes really grossly out. The change in IDSS with rising temp hits the TP voltage status. It does so bcs its a delicate balance disrupted by progressively stealing an amount of what bias current is channeled to the cascode BJT. Which in its own turn is small in comparison to what the two JFETs use. About 10% in the LMC config. In cold start the BJT current bias is at max. So no starving. Just asymmetrical voltage bias centering on the load resistor for large input signal transients to ride on until it warms up for 5 mins. If you can make a controlled K369s heat package somehow, its good for less variation across the load resistor. Thus less variation on TP readings. The K369s will still rise a bit IDSS as the heart of the chip inside gains temp by its own dissipation from cold. You hope to efficiently pull that heat away before it builds enough and to better isolate the external temperature dependencies at least.
 
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I got some "doubts" with my ambition to try to keep the hottest mosfets to the outside air and the rest of the comps to the EMI/RFI-sealed in case temp.

Since I think that to large differences between outside ambient and inside working temp can cause this problems I will give it a go annyway and see where I get. Large differences cause large fluctuations. The closer in-box temp to outside ambient the less fluctuations.

I understand that the "inner" mosfets, when boards are mounted side by side with DC in facing eachoter gets less heated. Is this true and how much? Can I use just a little smaller sinks for them (take one small wing off for size matters)?
 
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Materials that holds heat well (holds temp stable) has low thermal conductivity. In this case the material should lead away the heat enough to not overheat the K369s from its own generation but not dissipating it so fast that it cools them down too quick. No fins and not to high thermal conductivity and large in volume.

List of thermal conductivities - Wikipedia, the free encyclopedia.

Bronze, iron or lead maybe.

Copper 350-400
Brass 125
Iron, lead, bronze 30-70
Concrete 0,8-2,5
Plastics 0.0... -1
 
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If a resistor inside dissipates heat steadily so to create an oven less dependent to environmental changes it could be an interesting experiment. BJTs are no angels in such high gain input stage role also. They enclose them in the Paradise builds to help stabilize offset for instance.
 
There is no ID,TA,VGS crossing curves chart in their datasheet so I don't know. They could possibly never cross and always drift. It would take some trial and error when having a "summer house" for them.

Where I keep them it is almost always summer. My ambient have drifted between 20-28 degrees generally inside the house since last fall. The compartment temp near the 396's has moved between 28-38 degrees.

Starting when I have put voltage measurements to tp1 and tp2 on both channels I will measure these and the ambient and the enclosure for 1 year (when I can - of course - not the centre of my being :) ).
No sweat as I want to know and if SQ suffers during the year I have another Simplistic needing a build and other transports over other mediums - that I'm quite happy with :)

Regards
 
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I was thinking an appropriately sized piece of copper would both distribute and hold heat well. As Stajo says, less about dissipation and more about regulation. Funny bunch we are. Something like this RIAA sounds wonderful and we cannot even enjoy it:)

Materials that holds heat well (holds temp stable) has low thermal conductivity. In this case the material should lead away the heat enough to not overheat the K369s from its own generation but not dissipating it so fast that it cools them down too quick. No fins and not to high thermal conductivity and large in volume.

List of thermal conductivities - Wikipedia, the free encyclopedia.

Bronze, iron or lead maybe.

Copper 350-400
Brass 125
Iron, lead, bronze 30-70
Concrete 0,8-2,5
Plastics 0.0... -1

I've thought seriously about covering my dual 369's in a 100 percent silicon glop.
 
I've thought seriously about covering my dual 369's in a 100 percent silicon glop.

I can't say that log term changes has done anything with SQ - 28-38 degrees Celsius since last winter. I have a device measuring two temps, the internal in the case close to the 369's and the other almost at room temp. The latter showing maybe 1 degree more than room ambient.

I would rather not put too much effort into this as SQ is perfect at all times anyway. Maybe an temperature activated compensationary circuit would calm this down but I believe it would affect the circuit negatively.

I'll keep it as is for a time and rather learn how to keep the ambient stable.

Regards