Si570 based 2ps RMS low jitter universal audio clock project

[regal]

Si570 is a XO, while Si571 is a VCXO. It seems that 570 has better phase noise performance than Si571.

Here is the possible internal picture of Si570, hope you can get some idea from it.

Ian

And a XO will always have better performance than a VCXO, the nice thing about the FIFO is the buffer is big enough that a VXCO isn't needed. Its still a PLL in my mind just that the buffer is big enough that as long as the incoming clock is reasonable then the need for a VCXO is gone.

One thing I just can't help but mention is that to me we are better off just building a DAC have everything on one PCB with proper ground routing and signal transmission. I have two of your FIFO's now but just can't help but think I'd be better off if it was all on one PCB.

 

[qusp]

of course, but satisfying the many and varied tastes that make up the fifo users will be an impossible task and the development thread if there were one would be a war-zone... generally by the time youve gotten around to using the fifo in your DIY dac, youve already developed a taste for how you like things done.

honestly i'm not really sure it will provide enough higher performance having the fifo on the same PCB, given the trouble that is gone to, to isolate the fifo and clock from the source and it would want to be isolated from the vibrations of the dac and chassis

if you can palette the ESS then the upcoming ackodac super transport is pretty close