My SMPS is a boost with a SG3525 and 12Vin 14Vout. On OUT A I have a IRFZ48VS with a 220R gate resistor while OUT B is non connected. The problem is that the output of OUT A has short pulses while on OUT B there is a correct square wave.
Why?
Why?
This is because your out "A" is driving a resistive-capacitive load, while out "B" isn't loaded down at all. Assymetrical loads will yield assymetrical waveforms.
I know but,
the short pulse isn't capable of switching the mosfet and my smps doesn't work properly. Do I need a Rgate higher?
the short pulse isn't capable of switching the mosfet and my smps doesn't work properly. Do I need a Rgate higher?
Something is causing the IC to terminate the pulses prematurely when the IRFZ48 power stage is being driven. Check that the clock sawtooth is not disturbed, then check error amp output , sync pin and shutdown pin to see if a parasitistic signal in one of them is causing the pulses to be terminated too soon. It may be a problem related to the power supply of the IC or grounding too.
another question
In my boost (12Vin 13.8Vout) there are large voltage spikes (10-20V) on the mosfet drain when the mosfet turn off. What should I do?
In my boost (12Vin 13.8Vout) there are large voltage spikes (10-20V) on the mosfet drain when the mosfet turn off. What should I do?
One help is what I think you are already doing--adding together the alternating outputs, which lowers the peak current needed in each leg. Since your output voltage is less than twice your input, you may have a problem if your duty cycle is not less than 50% on each MOSFET. Still, your inductor probably needs to be quite saturation resistant.
One way I know for avoiding core saturation is a zero voltage switching circuit. Otherwise, it appears you will be operating in continuous mode where the inductor current continues in the same direction all the time, keeping your inductor core from magnetically resetting unless it is a type like air gapped or distributively gapped, eg., iron powder. Without such a core in a non-ZVS approach, the duty cycle needs to be very low unless you use a transformer with (a) secondary winding(s) having fewer turns than each primary. If you use a transformer, if you need a lot of output current, you will loose a lot of power in the rectifiers unless you use synchronous rectification.
If you use a transformer you will still have spikes on the drains of your MOSFETs to deal with, though. Just some possibilities to consider.
One way I know for avoiding core saturation is a zero voltage switching circuit. Otherwise, it appears you will be operating in continuous mode where the inductor current continues in the same direction all the time, keeping your inductor core from magnetically resetting unless it is a type like air gapped or distributively gapped, eg., iron powder. Without such a core in a non-ZVS approach, the duty cycle needs to be very low unless you use a transformer with (a) secondary winding(s) having fewer turns than each primary. If you use a transformer, if you need a lot of output current, you will loose a lot of power in the rectifiers unless you use synchronous rectification.
If you use a transformer you will still have spikes on the drains of your MOSFETs to deal with, though. Just some possibilities to consider.
Feedback SG3525
I am designing a feedback circuit for full bridge SMPS. Design include TL431 and optocoupler. Nowadays i researched lots of documents on web for finding clear information about compensation of feedback. Feedback is 2 pole 2 zero Compensation which is the best and hard one for designer i guess. According to books i am calculating zeros and poles, Some says zeros must be around esr and 1/2*pi*sgrt(LC) and poles must be around cross over frequency. What ever they are trying to say is not clear. My question is very simple. Why we are finding zeros and poles and using bode diagram?
I am designing a feedback circuit for full bridge SMPS. Design include TL431 and optocoupler. Nowadays i researched lots of documents on web for finding clear information about compensation of feedback. Feedback is 2 pole 2 zero Compensation which is the best and hard one for designer i guess. According to books i am calculating zeros and poles, Some says zeros must be around esr and 1/2*pi*sgrt(LC) and poles must be around cross over frequency. What ever they are trying to say is not clear. My question is very simple. Why we are finding zeros and poles and using bode diagram?
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