I was just reading the literature. They are acknowledging that a certain amount of gate current flows below the threshold voltage but not at the level of a BJT. I suppose a person would have to measure it to determine if it is a concern. I bet there is at least one person who has.
Papa sez - no gate leakage
Papa made paralleled Jfets in input LTP
I already wrote somewhere my reasoning for that - lower LTP drain resistance , due to lower Vgs of SS - means lower OLG
double input Jfets - double xconductance - even with wvwn lower Rdrain , means higher OLG
uh my brain is hurting .......
Papa made paralleled Jfets in input LTP
I already wrote somewhere my reasoning for that - lower LTP drain resistance , due to lower Vgs of SS - means lower OLG
double input Jfets - double xconductance - even with wvwn lower Rdrain , means higher OLG
uh my brain is hurting .......
it isn't matter of current , but xconductance ;
BL and V have comparable xconductance , even if Idss-es are in different groups
BL and V have comparable xconductance , even if Idss-es are in different groups
Very interesting! I remember reading a conversation about original SS fets (R125) having higher xconductance than the current 120R100's. Pass just made up difference in FE?
There is in fact Gate leakage, and devices should be tested
for excessive Gate current. Usually it's below about 20 uA
for this application, but I have seen a couple of parts that
were 10 times that. They work fine, but you have to make
an allowance for high Gate current when you have a high
impedance driving it.
😎
for excessive Gate current. Usually it's below about 20 uA
for this application, but I have seen a couple of parts that
were 10 times that. They work fine, but you have to make
an allowance for high Gate current when you have a high
impedance driving it.
😎
I don't recall that being the case. In practice I haven't seen
a significant difference.
😎
It's a legitimate question, and people have asked about the
differences between the two devices.
😎
What kind of heat can the SS devices tske compared to IRFP, and is it significant enough to provide advantages simply from a bias standpoint?
I thought i read somewhere that a higher bias sounds better. Problem is, it creates more heat. IRFP's can only take so much, so bias is limited unless using more devices. More devices, more noise. Device that can take more heat allows higher bias with fewer devices and less noise. This is a very uneducated answer, if not already apparent.
several times here is written that practical limit for mosfets is around 50W , if you use more powerful ones - IRFP150N per instance ;
there is no reason to torture other device in same package with more , even if that device is capable of taking more .
first important thing which is often neglected , in making any Papamp , is - one is making amp with original price above 2 or even 3K$ ( still bargain for that quality !) ....... and why skimping few $ , doing that ?
btw. "more devices - more noise " is wrong assumption
there is no reason to torture other device in same package with more , even if that device is capable of taking more .
first important thing which is often neglected , in making any Papamp , is - one is making amp with original price above 2 or even 3K$ ( still bargain for that quality !) ....... and why skimping few $ , doing that ?
btw. "more devices - more noise " is wrong assumption
I have yet to purchase the SS fets, but if I got them, it is pretty much just a matter of dropping them in to the lower half.
It's said that these FET's sound better at higher bias. Is this because we're operating them in a Vgs region that's more linear? Maybe because of a linearity that comes with increasing junction temperature? If there's no vague answer, then how about specifically the SS R100?
More specifically, they tend to measure less distortion at higher bias. That
is often interpreted as "sounds better"
😎
is often interpreted as "sounds better"
😎
