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Scalable PSU/regulator GB

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I have been using a 15VAC 50 VA transformer (Avel Y23 series from the group buy). That gives me around 21VDC input (11%regulation advertised). I see no problems until I drop the input voltage to around 13VAC. The oscillation bursts that I saw were 4-6mV P-P and at 250-300 kHz.

The residual noise in my scope is a couple mV so that may explain why I haven't seen the 5 MHz stuff. Time to upgrade my scope.

At 21V or above the oscillation does NOT occur.
If I shunt R4 with a 1µF capacitor the voltage drops to 18V

Jens - by this I assume that you mean there is no oscillation when R4 is bypassed with 1 µF as long as the DC input is above 18V. Just want to be sure 😉
 
Hi,
this is opposite to what Jens is finding
it is quite clear that when Vin is low and I lose regulation the oscillation disappears, at about Vt1=1V then 2mVpp, at Vt1=8V then osc=7mVpp.

I think it is some kind of instability.

Could it be worse when currents are lower?
I have not exceeded 250mA.

I have only used the lm4040-10

As said earlier, I used many ceramic in lieu of PES. Could this be aggravating the oscillation?
 
Hi,
success at all of 16.5Vac, 22.5Vac and 39Vac. Phew that was hard work. I can swing the output of low volts PCB from 14Vdc to 19Vdc using the 16.5Vac input. Ripple dips start at 19.2Vdc when Iout =190mA.

My boards look like a right bodge now but at least the 5MHz is now at 60kHz and of very low level, about 100uVpp to 200uVpp and very difficult (impossible) to lock on to. This is fairly consistent at all Vout between 15Vdc and 45Vdc.

However at the two higher AC inputs (the higher voltage PCB) there is leak through of 50Hz/100Hz sawtooth (about 200uVpp to 300uVpp). To get reasonable on load starting the r3:r4 ratio has to be compromised and with the higher resistances needed for a higher voltage board the r3 must be feeding dirty power to the Vref.

Noise, as near as I can see on my scope, never exceeds 300uV and may well be only half of that. It's worse at high voltage than at Vout=15V, where it is less than 100uV.

Come on you experts, design us a modification (that fits the PCB) to properly cure the start up sequence and keep r3's influence out of Vref.

Any repsonse to my previous thought of replacing D6 with a feedback capacitor? and relocating D6 elsewhere. Am I correct, will it will do it's job just as well under R4?

So my next job is to remove all the parallel components inserted under the PCBs (4 of them) and move all the bigger ones to top side. Then check for stability again.

Has anyone tied R4 to the output? I measure 0.2Vdc between the measuring end of R4 to the output terminal. By co-incidence or by design the same voltage as all the errors I am finding when measuring the output.

Somebody did not read Walt, ALW and Didden.
 
AndrewT said:

Has anyone tied R4 to the output? I measure 0.2Vdc between the measuring end of R4 to the output terminal. By co-incidence or by design the same voltage as all the errors I am finding when measuring the output.

I measure 9mV DC at 0.5A 15V out..... are you sure that you soldered everything or that the PCB does not have a badly plated hole?

9mV is not perfect I agree, but it is not a problem IMHO in this type of regulator. I'm sure the Jung regulator is better in this respect, but I'm unsure if it can be modified to generate 60V DC for the frontend of an amp.

\Jens
 
Hi Kro,
1uF polycarbonate (old stock that has the correct pin pitch and no longer available) across R4.

Still can't understand why we need to feed AC and other modulations into BOTH sides of the LTP amplifier. This solution completely defeats the whole philosophy of active modulation reduction (i.e. regulation).

Maybe a pair of caps of different types and values could achieve the stability requirements and still manage some level of active control/reduction.
 
Hi Jens & others,
that's a typo in post 384. Sorry.
The voltage difference should be 0.2mV = 200uV. (not 0.2V) at the measuring end of r4 to output terminal.

So your 0.9mV for the much higher output current seems proportional.

Have you also got about this level of artefacts (noise + ripple + sawtooth) superimposed on the output DC?
 
I'm sorry about that, I forgot to change my email address after I moved, it used to be my student one.
Try sdedalus83 at gmail dot com.
I'm interested in as many as 3 complete sets depending on price, with a minimum of 1 board and 1 parts kit.
 
Hi,
I forgot about this one (from a completely unrealated thread), since we don't refer to this in our thread.
one app where you should think twice about............. changin' the cap is in an low dropout regulator -- these have to be designed with the ESR of the cap in mind.

What limitations on output caps and combinations of caps would be needed to ensure stability at various loads?

The output current vs caps graphs given in LDO regulator data sheets are quite complex.
Are we into this region of operation?
 
AndrewT said:
The output current vs caps graphs given in LDO regulator data sheets are quite complex.
Are we into this region of operation?

Andrew,

Only if you run the regulator in "LDO mode"

The problem is that changes in ESL and ESR has a rather big effect on loop stability.

I hope to be able to do loop measurements when my day job stops taking all my time........

\Jens
 
Hi Jens,
this regulator is an LDO type.

It is the topology that determines whether it is conventional (EF) or LDO (common emitter).

The same rules on ESR will apply whether the volts drop across the pass device are just above the regulation limit or well above that limit.

It just happens that I would rather set my input voltage to ensure that at lowest mains input voltage (-10%) and maximum output current (0.2A) that the Pass device still has just enough regulation to ensure the ripple troughs do not pass through and this then determines the running input voltage based on normal mains voltage and normal/quiescent current demand. This philosophy then leaves the largest dissipation margin that can just cope with maximum input voltage (+6%) and just short of maximum current demand (I would need slightly larger heatsinks to cope with +6% and 0.2A if coincident.)

If you run with a normal 10 Volts across the pass device what happens when maximum input voltage coincides with maximum demand? Have you calculated, simulated or measured that senario yet?

Your statement
The problem is that changes in ESL and ESR has a rather big effect on loop stability.
hits my point exactly.

It then follows:- are the cap choices installed by Kro and myself causing the oscillation problem? These are output caps and feedback caps.
 
AndrewT said:
It then follows:- are the cap choices installed by Kro and myself causing the oscillation problem? These are output caps and feedback caps.

It would seem that a simple experiment might be in order. Try removing one half of the output caps (one electrolytic and one film) to see if this eliminates the oscillation that you are seeing. I wish I could see the oscillations you are. Car repairs just wiped out my new scope fund. 🙁


Has anyone else built/tested/used the regulator yet? (I remember Jacco and T. have at least bench tested)
 
BobEllis said:
Has anyone else built/tested/used the regulator yet? (I remember Jacco and T. have at least bench tested)
Built, used but only tested with a voltmeter. My (cheapo) scope returned from repairs just a few days ago, but I haven't had any time to verify this part of the discussion yet. Hope to soon, but chances are someone will beat me to it as I'm on a tight speakerbuilding schedule.

Hans.
 
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