Correct me if I´m wrong: When designing class A/B amps I need to be within the SOA curves, eventhough each transistor is only conducting ½ the time?
TroelsM
TroelsM
Hi,
YES stay within the SOA curves which are usually based on a case temperature (Tc) of 25deg C.
But there are many curves and all the faster ones require non-repeating pulses and these will not suit hi level bass signals.
I use DC values or 100mSec at worst.
I think you also need to reduce SOA values by the temperature reduction factor.
Combining these two factors can reduce a 250v device by upto 80% to 90% at 100v but much more favourable at 50v.
Do you want bullet proof / commercial / general domestic / Hifi?
regards Andrew T.
YES stay within the SOA curves which are usually based on a case temperature (Tc) of 25deg C.
But there are many curves and all the faster ones require non-repeating pulses and these will not suit hi level bass signals.
I use DC values or 100mSec at worst.
I think you also need to reduce SOA values by the temperature reduction factor.
Combining these two factors can reduce a 250v device by upto 80% to 90% at 100v but much more favourable at 50v.
Do you want bullet proof / commercial / general domestic / Hifi?
regards Andrew T.
Agreed. Worst case is a shorted output or a speaker-out signal crossing zero out of phase with max. current at 0V output... You will likely regret it more if you blow one up than if you spend an extra $10.
The project
I´m building a bridge amp with 6* TIP33C/34C in each half-bridge.
To make a stereo-amp that gives 24 TIP´s backed up by a 2*24V/620W transformer and the result should be around 2*150-200W/8ohm.
I would like the amp to be able to drive 8ohm speakers for PA use, but more likely it will only be used in a HIfi/Home-setup.
What do you think of this? Are the TIP´s to small or will it work?
As I see it the problem is the the current-capacity at 36V. It´s only 3A for the combined 3 TIP´s.
The complete schematics will be posted later, - I hope..
TroelsM
I´m building a bridge amp with 6* TIP33C/34C in each half-bridge.
To make a stereo-amp that gives 24 TIP´s backed up by a 2*24V/620W transformer and the result should be around 2*150-200W/8ohm.
I would like the amp to be able to drive 8ohm speakers for PA use, but more likely it will only be used in a HIfi/Home-setup.
What do you think of this? Are the TIP´s to small or will it work?
As I see it the problem is the the current-capacity at 36V. It´s only 3A for the combined 3 TIP´s.
The complete schematics will be posted later, - I hope..
TroelsM
Hi,
If your supply rails are running +-36v then to safeguard your output stage your short circuit protection must be less than 3A. To allow for imbalance between transistors and lack of accuracy in the set point I suggest you aim for 2A to 2.5A. This will strangle your bridged output!
Have you already bought the TIP's?
Buy something with a better 36v capability.
regards Andrew T.
If your supply rails are running +-36v then to safeguard your output stage your short circuit protection must be less than 3A. To allow for imbalance between transistors and lack of accuracy in the set point I suggest you aim for 2A to 2.5A. This will strangle your bridged output!
Have you already bought the TIP's?
Buy something with a better 36v capability.
regards Andrew T.
you've got a point but..
The short-curcuiet will be a VI-limiter-type. The currentlimit will be made dependent of the output voltage and therefore the current-limit will rise as the output voltage rise.
In this way the protection curcuit will keep the TIP´s within the SOA and not "just" limit the current.
The simulation shows that it should be possible to drive a 4ohm load with the bridge, but that would push the TIP's to the limit.
TroelsM
The short-curcuiet will be a VI-limiter-type. The currentlimit will be made dependent of the output voltage and therefore the current-limit will rise as the output voltage rise.
In this way the protection curcuit will keep the TIP´s within the SOA and not "just" limit the current.
The simulation shows that it should be possible to drive a 4ohm load with the bridge, but that would push the TIP's to the limit.
TroelsM
If you are designing down to the wire, using cheapest possible components, then paradoxically SOAR constraints are very important.
Consider worst case with a 4R nominal load. With 36V rail, 4A would imply 16V at the load, and thus 20V across the device. These days, this is not so unrealistic, and if you stick with your 36V rails, use 230V transistors like the 12A 2SC5200/2SA1943, then SOAR failures are extremely unusual and you can often avoid the complexity of protection, which frequently has intrusive sonic effect. In the eighties manufacturers eschewed protection at their risk, but these days it's fairly common, and even practical when aiming for highest possible fidelity.
Cheers,
Hugh
Consider worst case with a 4R nominal load. With 36V rail, 4A would imply 16V at the load, and thus 20V across the device. These days, this is not so unrealistic, and if you stick with your 36V rails, use 230V transistors like the 12A 2SC5200/2SA1943, then SOAR failures are extremely unusual and you can often avoid the complexity of protection, which frequently has intrusive sonic effect. In the eighties manufacturers eschewed protection at their risk, but these days it's fairly common, and even practical when aiming for highest possible fidelity.
Cheers,
Hugh
I know but..
The TIP's are free (to me, at least) and that's the main reason for using them. I know they are not very good at this "high" voltage, but still it should work.
TroelsM
The TIP's are free (to me, at least) and that's the main reason for using them. I know they are not very good at this "high" voltage, but still it should work.
TroelsM
I am using "TIP141/146" devices in a class G amp and have to use 3 pair (as top drivers) to drive a pair of high current outputs. They were cheap🙄 and I expected I might "experiment" and blow a few. The SOA is not so great on these devices. In addition to that, the TIP141's that I got are fakes.😡 and have an even lower SOA, obviously. 
So I had to triple them up, temporarily. I will get some better parts in the future and use just two paralell. Until then, it still cranks a LOT louder than I will listen. (and that's just one channel)😀 😀 , just doesn't look as pretty.
So I had to triple them up, temporarily. I will get some better parts in the future and use just two paralell. Until then, it still cranks a LOT louder than I will listen. (and that's just one channel)😀 😀 , just doesn't look as pretty.
Here's a discussion, but he does not cover an interesting issue with higher voltages across power transistors. Note how much power, even at Tj=25, the MJL devices will handle first at 50V then at 100V both within the max Vce, do you know what's going on:
http://sound.westhost.com/soa.htm
Maybe you've already seen this page, the pictures of melted transistors should be a warning. He also suggests designing for 8/4 ohms, most good high current designs handle 2 ohms even lower.
This analysis for the ETI-466 amplifier might also help as an example:
http://www.alphalink.com.au/~cambie/ETI466App1a.zip
http://sound.westhost.com/soa.htm
Maybe you've already seen this page, the pictures of melted transistors should be a warning. He also suggests designing for 8/4 ohms, most good high current designs handle 2 ohms even lower.
This analysis for the ETI-466 amplifier might also help as an example:
http://www.alphalink.com.au/~cambie/ETI466App1a.zip
AndrewT said:
This is incorrect....power transistor FBSOA characteristics are based in fact on Tj~150degC...which should never be exceeded....
See pg. 7 here:
http://www.onsemi.com/pub/Collateral/AN1628-D.PDF
PB2 said:
Thanks for pointing this out Mikeks, the SOA chart at that site does show Tj=25 degC and I checked the original data sheet but I think it's a mistake, most others are Tj = 150 degC or Tj(pk)=200. BTW, I would not want devices at Tj=200. Most SOA curves do state Tc = 25 degC and there is a power derating curve for increased Tc. No doubt that's a misprint on that data sheet.
Hi,
Mikeks, thanks for taking the time to read my notes.
Please confirm again that the SOA curves are based on Tc=25degC or Tj<=150degC or both at the same time?
regards Andrew T.
Mikeks, thanks for taking the time to read my notes.
Please confirm again that the SOA curves are based on Tc=25degC or Tj<=150degC or both at the same time?
regards Andrew T.
Typically, Tj(max)=200deg. C (Metal case) or Tj(max)=150deg. C (Plastic case).
It is at these maximum ratings that FBSOA characteristics are obtained.
Additionally, the FBSOA characteristic (alias: max. permissible power dissipation Pd) is usually specified at case temp. Tc=25 deg. C, i.e: With an 'infinite' heatsink, (realised in practice by a constant spray of cold water).
The later of course, is of little more than academic interest to the user, (who's very unlikely to require Pd(max) from a single device), unless the junction-case thermal resistance R(j-c) is absent from the device's data sheet.
In which case, R(j-c) may be straightfowardly obtained from:
R(j-c)=(Tj-Tc)/Pd
The users (alias: designers) sole objective in this regard is to provide sufficient heatsinking to ensure Tj<=150deg. C(plastic case) at the system's ambient temperature, (typically 50 deg. C).
Derating is only necessary if the designer is unwilling or unable to provide enough paralleled devices, and/or sufficient heatsinking (or other 'thermal management'), to guarantee Tj<=150deg. C(plastic case) for each of his/her transistors at his/her system's ambient temperature.
It is at these maximum ratings that FBSOA characteristics are obtained.
Additionally, the FBSOA characteristic (alias: max. permissible power dissipation Pd) is usually specified at case temp. Tc=25 deg. C, i.e: With an 'infinite' heatsink, (realised in practice by a constant spray of cold water).
The later of course, is of little more than academic interest to the user, (who's very unlikely to require Pd(max) from a single device), unless the junction-case thermal resistance R(j-c) is absent from the device's data sheet.
In which case, R(j-c) may be straightfowardly obtained from:
R(j-c)=(Tj-Tc)/Pd
The users (alias: designers) sole objective in this regard is to provide sufficient heatsinking to ensure Tj<=150deg. C(plastic case) at the system's ambient temperature, (typically 50 deg. C).
Derating is only necessary if the designer is unwilling or unable to provide enough paralleled devices, and/or sufficient heatsinking (or other 'thermal management'), to guarantee Tj<=150deg. C(plastic case) for each of his/her transistors at his/her system's ambient temperature.
derating
It sounds as if your suggesting that derating is the exception rather than always required with passive cooling, am I reading you correctly?
mikeks said:
It sounds as if your suggesting that derating is the exception rather than always required with passive cooling, am I reading you correctly?
Depends on application and cost-benefit trade-offs.....
Derating reeks of cheopo (read: unacceptable) engineering....as far as power amps are concerned anyway....(methinks)
Personally, would prefer to use sufficient heatsinking with more than enough transistor pairs to render derating unnecessary....
Derating reeks of cheopo (read: unacceptable) engineering....as far as power amps are concerned anyway....(methinks)
Personally, would prefer to use sufficient heatsinking with more than enough transistor pairs to render derating unnecessary....
Hi,
to achieve good reliability you must not exceed the manufacturers ratings.
If the case temperature is above 25degC then you must derate according to the manufacturers instructions. If you follow this you will also stay within Tj limits.
For good reliability most recommend that you do not exceed Tj of 125degC.
regards Andrew T.
to achieve good reliability you must not exceed the manufacturers ratings.
If the case temperature is above 25degC then you must derate according to the manufacturers instructions. If you follow this you will also stay within Tj limits.
For good reliability most recommend that you do not exceed Tj of 125degC.
regards Andrew T.
AndrewT said:
Hi Andrew.....I fully understand your confusion.....
The case temperature MUST remain at 25 deg. C if and ONLY IF a transistor rated at say 200W, is in fact required to dissipate 200W.
Otherwise, if higher Tc anticipated for this dissipation (as is always the case), then you MUST derate...
But...in what application would you require that a SINGLE device be provoked into dissipating this amount of power, without it having been shared out between paralleled devices?
Example:
(200W/5 pairs)=40W per 200W device!!
With proper heatsink, NO derating required, case temperature can now be well above 25 deg. C per device with no problem!
Alternative approach....
If a transistor rated at 200W, for Tj=150 deg. C, and Tc=25deg. C, is only allowed to dissipate Pd=40W max.
What will Tj=? for this 40W, assuming Tc=70 deg. C?
If a transistor rated at 200W, for Tj=150 deg. C, and Tc=25deg. C, is only allowed to dissipate Pd=40W max.
What will Tj=? for this 40W, assuming Tc=70 deg. C?
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