S/PDIF input problem

370mV is the drop-out voltage. That's the minimum voltage drop across the regulator where it can still regulate. However, that's not the voltage drop that will probably be across it in most cases.

Let's say you have a transformer, rectifier and filter cap that put out 9.3 VDC. Let's also say the regulator output voltage is going to be 5V. Then the voltage drop across the regulator will be 4.3V.
 
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More or less, yes. There should be enough headroom to allow for normal line voltage variation, for transformer regulation, filter cap voltage droop, etc. Also depending on audio circuitry, voltage regulators may have some affect on sound. IOW, voltage regulator circuitry may not be fully decoupled from amplifier circuitry, rather they may interact in some way that affects sound. In that case, some regulators have been known to sound best with sufficient voltage drop and or sufficient load current. However, in this case it doesn't seem like you are being all that very picky about sound, so some of more subtle stuff may not applicable here.
 
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Well I am picky about quality to an extent🙂 Im not building high end, but a decent system. I have separate supply for DAC only and it will be isolated from digital part. Now making PSU for digital only (as its terrible at the moment), think this approach is correct?

Also would you take this IC in my place? Go with SMPS instead?
 
Okay. Sounds like DSP is I2S bus master for RPi GPIO bus? What about the dac clock, where is it? Is it also the reference clock for the DSP? Also, the isolators are between the dac and the DSP? Maybe it would be easier to see if there were a little signal flow diagram that also shows isolators and power supplies?
 
May not be relevant but have you got a DC coupling capacitor in line on the shark dsp spdif input? On the ADAU14xx chips the spdif input is at half VCC and needs one to block the DC.
You mean this one?
1683376637967.png
 
DSP is master, rest of devices are slaves,
Still not quite clear. Master and slave terminology usually refers to I2S bus clocks (LRCK, BCLK). The reference or master clock may be referred to as MCLK. For 96kHz sample rate operation, MCLK might be something like 12.288MHz or maybe a multiple of that, say, perhaps 24.576MHz. In that regard ESS dac chips are different than most because they have internal ASRC, which can allow them to run on more or less arbitrary MCLK frequencies (so long as MCLK is in the range specified in the ESS datasheet).

So, part of my question was about MCLK. Is there only one for the whole audio system and it is located on the DSP board?

EDIT:
Regarding DC blocking for sharc chip SPDIF inputs, the following diagram can be found in: https://www.analog.com/media/en/technical-documentation/application-notes/ee.266.rev.2.08.07.pdf
1683539006006.png
 
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