Ripple current rating of paralleled caps

In a parallel network the individual currents of the parallel elements add up together. Since the resultant current is the sum of individual currents, ripple currents are also added. This means the resultant ripple current is the sum of individual ripple currents. To equally share currents the individual capacitors have to be identical in value and make.
 
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If there is let's say 4A ripple current with a given capacitance and ESR, that 4A can go to 1 cap (single cap design) or be shared by parallel caps (in a parallel cap design).
Current will take the path of least resistance (as everything in nature), so if the caps are equal in all respects, as is the resistance of the wiring (equal lengths and wire type), the current will be equally shared by the capacitors.
So, in a good 5 cap design, each capacitor would see 1/5th of the total ripple current.
 
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According to Kirchhoff's law, the ripple current will be distributed by the inverse of the capacitors' impedance, which at a given frequency is inversely proportional to their capacitance values. This explains exactly the nonsense of paralleling capacitors of different (by magnitudes) values in PSU (and other) applications.

Best regards!
 
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Reason for asking...I'm considering building an offboard PSU for a class A amp (M2X) and the reasons for this are 2 fold.
1. It removes the potential for interference from the AC transformer in the PSU to the signal transformer on the M2X boards.
2. I would go trafo/rectifier/ initial DC smoothing with some big (22 or 33mgmf caps; 1 per rail; close to the rectifiers. All in one chassis. Then umbilical to the amplifier with then local onboard capacitance using Prasi's Cap Bank PCB. Here I can fit 12 caps, 6 per rail. I have some 10000uf caps for this and their ripple current rating is about 3 amps at 50hz.
My thinking being this will give a a good low impedance supply next to the amp channels.
 
Makes sense, as it's always helpful to get PSU capacitors as close as possible to the power sink, hence decouple the umbilical's resistance/impedance in your arrangement. But remember that 100 Hz ripple current doesn't need to leave the PSU section. You're going to decouple the signal ripple.

Best regards!
 
Just a few things to consider. I am not familiar with Prasi's Cap Bank pcb, so will assume there is not active (e.g. cap multiiplier) or passive (R or L) smoothing involved.

If you design it as C in the psu box and C in the amp box, then you have effectively created a CRC psu, with the resistance of the umbilical (+ resistance of connectors etc) being the R in CRC.
If the resistance between the caps in the psu box and the cap in the amp box was zero (which it cannot be), the caps would be logically parallel. As the resistance cannot be zero, this is not a case of parallel capacitors.

In a CRC psu, the first C is stressed much harder (much bigger ripple) than the second C. Something to consider!

I would advise to download PSU Designer II https://www.duncanamps.com/psud2/
Play around with different values for C (check ESR from the datasheets) and R and see for yourself how big the ripple at the first and second C will be.
 
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Thanks for that reply Albert (?).
So my reference to parallel is just the caps in the cap bank and indeed to L or R. And yes I understand I shall create a the CRC by virtue of the resistance of the umbilical. And yes the 2 caps in the PSU section would be beefier than the ones in the AMP section. I have some learning with PSUd. Have played with it before but didn't get out of the starting blocks. And I can't find the esr of these 10000uf caps. Tried to measure with my der-5000 but it reads zero so must be low!
 
No, I meant make sure that the ripple in the first bank is not higher than the rating of the capacitor(s) in the first bank. You would be surprised how big that ripple can get!

Please download psu designer. Test it with:
  • C 40000 (i.e. one capacitor bank)

and test again with two other examples:
  • C 20000 0R001 and C20000 (i.e.CRC with low R)
  • C20000 10R and C20000 (i.e. CRC with high R)

Using extreme examples (0R, 0R001 and 10R) should give you some idea how a small change can make quite a difference.
You can then play around with the capacitor arrangement (e.g. from initial 20k R 20k to
  • 10k R 30k
  • 1k R 39k
  • 39k R 1k
  • etc.
It will let you see the ripple at the first C but also what ripple you can expect at the amp input.
Use a suitable R to simulate the load using V/I=R, where V is the rail voltage and I is the current drawn (for simulations, just use to the bias current).
 
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Thanks for that reply Albert (?).
So my reference to parallel is just the caps in the cap bank and indeed to L or R. And yes I understand I shall create a the CRC by virtue of the resistance of the umbilical. And yes the 2 caps in the PSU section would be beefier than the ones in the AMP section. I have some learning with PSUd. Have played with it before but didn't get out of the starting blocks. And I can't find the esr of these 10000uf caps. Tried to measure with my der-5000 but it reads zero so must be low!
ESR should be in the datasheet. I recently had to check ESR of some 30 year old caps that needed replacing and was amazed how high they were compared to the new low impedance United Chemicons I was planning to use.
I have never tried to measure ESR, so have no idea how. I just rely on the datasheets.

PSU designer really is worth spending half an hour on.
 
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Perhaps your focus should be to separate the power supply C from the local amp C, such that minimal rectifier ripple flows through the local amp C, and minimal local amp signal current flows through the rectifier C. The harder current flow to isolate is the local amp signal current, as it may have a frequency range from well below twice-mains frequency, to well into the tens of kHz.

Another aspect to focus on is how well the amp rejects AC voltage on its power supply, as that imho should drive the level of mF used, rather than some ill-defined level with no rational reasoning.