Oh, absolutely. I notice most people only use one side of the PCB.
If you intentionally use both sides, at least four layers there is a lot of stuff that can be optimised differently.
Not all components are asymmetrical. I favour those that are.
Take the 16 bit parts I have been mentioning.
There are symmetrical "feed through" type SMD capacitors that fit below the PCB onto the two GND and the single VCC pin.
Now everting in power supplies idles symmetrical. Idles the chip itself symmetric on a die level? Knowing human tendencies, probably, especially as these 16 bit parts are explicitly marketed as designed to have minimum skew between invidial pins.
Using both sides is really only possible with SMD. Symmetry may be of interest, but as alternative angle, take something like a large QFP Chip with many PSU and GND Pins and pins for core power, multiple PLL's (VCO's, must be low noise) and multiple I/O banks.
If you put the decoupling around the IC on the top, you end up with a lot of PCB area and quite long loops. Decoupling efficiency is poor.
Place the capacitors below the IC, voila, much shorter loops, much better decoupling efficiency.
Well, after "getting" H. Ott I might demure on that point. His book and various articles are massive BFO's of stuff that we all "know" but kind of forget, don't really get etc. et al.
Ultimately it all comes back to current loops and Kirchhoff and is really simple.
Radiated EMI requires making pretty basic mistakes. If all current loops are controlled correctly and currents go where they should, they cannot radiate into space...
Thor
Ummm, we know whip antennas can radiate. Thinking its not quite so simple as you seem to be saying. IOW, in the nearfield there are EM fields that can be mostly magnetic or mostly electric. If they radiate off into space then in the far field they balanced according to the characteristic impedance of free space. In the intermediate field is where it gets more complicated.
Also, one has only to clip the ground lead the tip of a scope probe, the wave the ground lead over the top of a dac chip. All kinds of garbage is to be found. An E-field probe with an RF spectrum analyzer can find garbage in all sorts of place. So part of the problem is susceptibility local fields.
Now perhaps consider that many good sine wave squaring circuits are high gain RF amplifiers. The amplify so much the sides of the sine waves may have .5ns risetimes. Get a tiny RF electric field antenna near that, and maybe some unwanted interaction can take place?
Moreover in a lab setting, getting a USB board too near a dac chip can start affecting the sound. USB boards tend to radiate most off of the component side and least off the bottom ground plane side. IME its often best to put the USB board under the dac board with both of their bottom ground planes facing each other.
Of course, things should be different in a final product design than in a lab experiment. However in this case here, IMHO there are some more lab studies to be done with Marcel's dac board before trying an overall redesign. Even then if its not a totally integrated design then there may still be some lab setting considerations to contend with.
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OK, let me get this straight: we are now discussing how a design that has had components on both sides of the board from the very beginning would improve if only it had components on both sides of the board? 😉
Seriously, it is very possible that the use I decided to make of the two board sides and the shielding layers in between is suboptimal. By lack of sufficiently accurate models of the SN74LV574A or whatever replaces it, I think the only way to find that out is to make several PCB designs, have a couple of each manufactured, mount components on them and test them. I have no intention to do that, but if anyone else wants to try, they have my support.
Seriously, it is very possible that the use I decided to make of the two board sides and the shielding layers in between is suboptimal. By lack of sufficiently accurate models of the SN74LV574A or whatever replaces it, I think the only way to find that out is to make several PCB designs, have a couple of each manufactured, mount components on them and test them. I have no intention to do that, but if anyone else wants to try, they have my support.
What is the goal of all these suggested layout changes? What deficiencies need fixing?
Original output stage works well apart from slightly elevated distortion at higher audio frequencies. Alternatives for improving that have been presented and some of those are already in use.
Add-on stuff like reclocker is not a revelation as it has been shown to improve performance of this dac aions ago in this thread and have been used by some ever since.
IME most impact comes from the modulator. With suitable modulator (e.g. HQPlayer AMSDM7 or SDM6/8 in sox) performance and sound is good. PCM2DSD in its current state is not up to the task with this dac.
Painting this dac as potentially the best sounding DIY dac is a bit far-fetched. There are many other good DIY dacs in this site. It is not even the best DIY dac I have. But no doubt it can be still improved in many ways. However I doubt this kind of thread is a proper way to progress things as consensus cannot be reached on technical matters and especially not on subjective matters such as good sound. So for those suggesting improvements Marcel's post #3425 sums it up nicely.
Original output stage works well apart from slightly elevated distortion at higher audio frequencies. Alternatives for improving that have been presented and some of those are already in use.
Add-on stuff like reclocker is not a revelation as it has been shown to improve performance of this dac aions ago in this thread and have been used by some ever since.
IME most impact comes from the modulator. With suitable modulator (e.g. HQPlayer AMSDM7 or SDM6/8 in sox) performance and sound is good. PCM2DSD in its current state is not up to the task with this dac.
Painting this dac as potentially the best sounding DIY dac is a bit far-fetched. There are many other good DIY dacs in this site. It is not even the best DIY dac I have. But no doubt it can be still improved in many ways. However I doubt this kind of thread is a proper way to progress things as consensus cannot be reached on technical matters and especially not on subjective matters such as good sound. So for those suggesting improvements Marcel's post #3425 sums it up nicely.
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Just Idle speculative talk about how things might be
As I pointed out, the 22uF capacitors, despite being already "inductive" provide still a relatively low impedance up to 100MHz.
Given that we are clocking the Shift registers with appx. 25MHz one needs to decide if this is adequate or not.
Personally I would probably use multiple identical value l, lower value capacitors with much smaller physical size and higher quality dielectric to reduce microphonics (see H. Ott - OMG - I start sounding like the late Pat DiGiacomo aka. Jocko Homo - I need to stop that).
But clearly you analysed (and measured?) the actual design in detail and found the current solution adequate to meet your design goals.
Thor
Surely you do not design whip antenna's onto your PCB's? (trick question).
If you design your PCB's (for CMOS logic) according to H.Otts recommend practice, all high speed traces end up buried and located between the Vss and Vcc planes to provide correct current path for return currents.
If you instead put ferrites onto exact IC's supply line, with a single 0.1uF decoupling capacitor and then place tour trace on the outside layers of the PCB, preferrably at a large distance from the ground plane, yup, you end up with a PCB full of whip antenna's and signals with nanoseconds rise time into these.
But whould do such a thing? Ok, I did it, before I read Ott.
Thor
Actually Ott listed 6 multilayer board objectives one of which was what you mentioned. He also stated that not all objectives can be met especially with a board having 4-layers so compromises are needed. He also stated that from both an EMC and signal integrity point of view burying signal traces between planes is not the most important objective.
Still thinking current loop routing can sometimes be more complicated than some may suggested, at least if the number of layers is limited due to cost factors.
For example, it may be hard to keep current loops as small as possible when clock signals have to be routed to devices across circuit boards. Here is a short excerpt from LTC6957 data sheet:
Timing jitter is a term used to describe the integration of phase noise over a specified bandwidth which is presented as a time domain specification. Unfortunately, the term “low jitter” has become so overused that it is rendered virtually meaningless. High speed communication links doing de-serialization and the like can require jitter on the order of 30ps to 50ps. This is lower jitter than required for a clock on a micro-controller, but for high frequency sampling, even 1ps can severely impact the dynamic range achievable. Therefore, it is best to ignore the term “low jitter” and look for measured values of jitter, and preferably phase noise. To analyze and measure true low noise components, most instruments measure phase noise (in dBc/Hz) rather than jitter.
A second consideration when designing for low phase noise is that any clock signal is an analog signal and should be thought of and routed as such. They should not be run through large FPGAs with lots of activities at multiple frequencies, they should not be routed through PCB traces alongside digital data lines, and they should not be routed through clock fan-out devices that have features such as zero delay or programmable skew. The specifics of the PCB traces and what surrounds them should be analyzed as if the clock signals were among your most sensitive analog signals, because in demanding applications that is what your clock signals are.
Note that signal integrity software intended for analyzing crosstalk in digital systems may only give yes or no answers and that clocking performance can be compromised at levels 40dB to 60dB below what is required to get that “yes” answer. Common pitfalls with clock signals are the same as for sensitive analog signals: routing near or alongside digital traces of any kind, crossing digital traces on an adjacent layer within a sandwich of ground planes, using digital power planes as part of layer sandwiches, and assuming all of these are sufficiently mitigated by using differential clock signaling. The way to address these issues is also the same as for sensitive analog signals: routing away from digital traces wherever possible; routing with shielding of ground, either planes, adjacent traces, or both; making realistic assumptions of common mode rejections (30dB to 40dB at most); and keeping a critical eye out for unintended couplers during the design and debug phases.
For myself anyway, I notice very small levels of phase noise problems in high resolution audio dacs such as Marcel's RTZ dac. The boards I designed in another thread can be used to demonstrate to the effects of phase noise sensitivity resulting from the choice of small signal operating point of a local IC voltage regulator (which most designers completely miss).
A board peppered with small ceramic caps is a complex piezoelectric noise generator in the presence of vibration caused by loud reproduction of music. Even in the absence of vibration, nonlinear bypass caps have been observed to have a deleterious effect on phase noise.
Ferrite beads destroy ultra-low phase noise whether or not it looks like it on a phase noise analyzer. Its easy to demonstrate experimentally. As I said in one post in that other thread, "...I am persuaded by the physical evidence rather than what looks to me like oversimplified theory..." https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/post-7729193
Anyway, I feel more or less similarly in this situation. Hopefully, more people will start to understand the above issues if and when they successfully implement what I have shown how to do with Marcel's dac. Just try it and see, would be my stance.
For example, it may be hard to keep current loops as small as possible when clock signals have to be routed to devices across circuit boards. Here is a short excerpt from LTC6957 data sheet:
Timing jitter is a term used to describe the integration of phase noise over a specified bandwidth which is presented as a time domain specification. Unfortunately, the term “low jitter” has become so overused that it is rendered virtually meaningless. High speed communication links doing de-serialization and the like can require jitter on the order of 30ps to 50ps. This is lower jitter than required for a clock on a micro-controller, but for high frequency sampling, even 1ps can severely impact the dynamic range achievable. Therefore, it is best to ignore the term “low jitter” and look for measured values of jitter, and preferably phase noise. To analyze and measure true low noise components, most instruments measure phase noise (in dBc/Hz) rather than jitter.
A second consideration when designing for low phase noise is that any clock signal is an analog signal and should be thought of and routed as such. They should not be run through large FPGAs with lots of activities at multiple frequencies, they should not be routed through PCB traces alongside digital data lines, and they should not be routed through clock fan-out devices that have features such as zero delay or programmable skew. The specifics of the PCB traces and what surrounds them should be analyzed as if the clock signals were among your most sensitive analog signals, because in demanding applications that is what your clock signals are.
Note that signal integrity software intended for analyzing crosstalk in digital systems may only give yes or no answers and that clocking performance can be compromised at levels 40dB to 60dB below what is required to get that “yes” answer. Common pitfalls with clock signals are the same as for sensitive analog signals: routing near or alongside digital traces of any kind, crossing digital traces on an adjacent layer within a sandwich of ground planes, using digital power planes as part of layer sandwiches, and assuming all of these are sufficiently mitigated by using differential clock signaling. The way to address these issues is also the same as for sensitive analog signals: routing away from digital traces wherever possible; routing with shielding of ground, either planes, adjacent traces, or both; making realistic assumptions of common mode rejections (30dB to 40dB at most); and keeping a critical eye out for unintended couplers during the design and debug phases.
For myself anyway, I notice very small levels of phase noise problems in high resolution audio dacs such as Marcel's RTZ dac. The boards I designed in another thread can be used to demonstrate to the effects of phase noise sensitivity resulting from the choice of small signal operating point of a local IC voltage regulator (which most designers completely miss).
A board peppered with small ceramic caps is a complex piezoelectric noise generator in the presence of vibration caused by loud reproduction of music. Even in the absence of vibration, nonlinear bypass caps have been observed to have a deleterious effect on phase noise.
Ferrite beads destroy ultra-low phase noise whether or not it looks like it on a phase noise analyzer. Its easy to demonstrate experimentally. As I said in one post in that other thread, "...I am persuaded by the physical evidence rather than what looks to me like oversimplified theory..." https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/post-7729193
Anyway, I feel more or less similarly in this situation. Hopefully, more people will start to understand the above issues if and when they successfully implement what I have shown how to do with Marcel's dac. Just try it and see, would be my stance.
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Correct. Which idles why nowadays use 6 - 8 layers for highish speed logic boards.
Yes, the best compromise is not to use 4 layers except for slow audio signals.
No, but once the basics have been covered, it's the next step that dramatically cuts EMI. I used to have access to an EMC test chamber and the necessary probes and 5GHz RF Analyser while at ifi/AMR. So I got to test a fair bit.
Passing certification is possible on a well designed 4 layer board, but a well designed 8 layer board with all high speed traces buried is on another level. For non EMI/EMC related issues as well.
The reason for high speed traces to be wedged between Vcc and Vss (note, I do not use "GND" is the peculiar nature of CMOS logic.
The NMOS "pull down" switches are referenced to Vss, while the PMOS "pull up" devices are referenced to Vcc. So both Vcc and Vss are signal reference points and each devices input capacitance is actually distributed with one part references to Vcc and another (often larger) part to Vcc.
So the current loops that develop with a tetminated strip line to a CMOS IC input include both Vcc and Vss. Having both planes running with the signal ensures "best case".
It really shows up in jitter measurements.
While 6 or 8 layer boards are little more expensive than 4 layer, in context, including all other factors, including our own labour cost, they are cost efficient.
Thor
Yes the crystal is sensitive too. However, even if the crystal is well protected, routing signals from there to another board in the lab shows the other board can damage phase noise locally if nonlinear bypass caps are used.
Also, I should mention that at this point I am primarily interested in finding out how very small phase noise problems can affect dacs. I am not focused right now on design for emissions compliance, which is not as much of concern for diy builders as it is for commercial designers.
IOW, what I want to focus on at this point is to find a benchmark, a point of reference for what preserving ultra-low phase noise can potentially do. Implementing compliance without damaging phase noise could turn out to take a fair bit more work.
Also, I should mention that at this point I am primarily interested in finding out how very small phase noise problems can affect dacs. I am not focused right now on design for emissions compliance, which is not as much of concern for diy builders as it is for commercial designers.
IOW, what I want to focus on at this point is to find a benchmark, a point of reference for what preserving ultra-low phase noise can potentially do. Implementing compliance without damaging phase noise could turn out to take a fair bit more work.
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Well, by looking at device geometries, capacitor physical sizes etc. and edge rates (or slew rate) of the outputs we can infer a lot.
If (for arguments sake) we replace the dual 74XX574 with a single SN74AHCT16374DGV, in TVSOP48 with 8 GND (Vss) and 4 Vcc pins we have much smaller loop areas for power and grounds and a symmetric IC layout (if the die is symmetrical, who knows, though claims on match between individual flip flops suggest so)...
And if (for arguments sake) we place 4pcs of Johanson Dielectrics 160X41W105MV4E 3-Terminal X7R capacitors adjecent to the relevant pins with minimum spacing possible and plenty of via's into relevant planes, so we get an effective decoupling range from < 3MHz to > 80MHz...
And if (for arguments sake) we then place 22uF 1210 capacitors to the left/right of the IC with prenty of Vias into planes, bury the signal traces and place a solid ground plane under the IC...
And if (for arguments sake) we wire up the 16 Element Flip Flop suitably interleaved to match your design...
I would suggest that it is hard to argue that the current design with 74XX574 and 22uF 1210 as sole decoupling will offer superior performance. Will my suggested design perform better? I have some reasons to consider it might, simply by looking at the frequencies and rise times involved in the circuit.
Even just switching from SSOP20 with ~12mm distance between the Vcc and Vss Pin to TVSOP (~8mm) or better VQFN20 ( ~4mm) with the same decoupling capacitor below the IC would show improvements, switching from one large value with a very large loop area and size low grade ceramic MLCC to multiple smaller value, size and higher grade MLCC below the PCB we can "see" improvements in signal integrity by observing the reduced loops.
So we can probably do a lot in a simple deductive reasoning, to reduce the number of options to try.
This all the more so if we look to have the PCB's made and assembled by someone like JLCPCB so we do not need to hand assemble tiny SMD components.
Thor
Class 1 ceramic capacitors are neither non-linear nor piezoelectric.
Who has observed and where?
Well, how about demonstrating?
I usually use perfboard for slow audio signals, or dead bug style mounting above a ground plane. It's much easier to modify things like that, unfortunately it is not very suitable for SMDs.
You are quoting me out of context. The context was whether it is a good idea to mount half the shift register on the bottom side, thereby improving symmetry, but giving up on the idea to keep all data handling circuitry except the actual FIRDAC on the bottom and all clock and reference-related circuitry on the top to reduce data to clock and reference crosstalk.
Doesn't sound like DIY to me.
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Anyone can demonstrate for themselves once they have a Marcel RTZ dac with ultra-low phase noise. Plenty of ways to play around messing it up. However until someone has a good enough dac like Marcel's with ultra low close-in phase noise clocking, they probably have so many phase noise problems already that one more small difference might not even be noticeable.
Someone could call the quote from LTC6957 data sheet in #3,449 an unsubstantiated claim. Maybe it would say more about the person attacking the quote than it would say about the accuracy of the quoted information itself.
EDIT: BTW, this type of conversation not new. Years ago I was asked to record the sound of a dac playing back so that other forum members could play back the recording on their own dacs to see if my dac was really better than their own dacs.!!? IOW, it made no sense whatsoever, but they couldn't understand why it wouldn't work. Now its a few years later and I'm feeling like its the same old same-old. Demonstrate how? By making a recording?
EDIT: BTW, this type of conversation not new. Years ago I was asked to record the sound of a dac playing back so that other forum members could play back the recording on their own dacs to see if my dac was really better than their own dacs.!!? IOW, it made no sense whatsoever, but they couldn't understand why it wouldn't work. Now its a few years later and I'm feeling like its the same old same-old. Demonstrate how? By making a recording?
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