i was wondering the same thing.
I will eventually get one of these and run it more normally than I did my first board! Will use regular supplies and dispense with the batteries. I think the batteries are superior but I do not want the hassle for what I suspect would now be a negligible difference.
I am curious about trying out the balanced configuration. But I have not read much user comments about this other than jjanssen's 1541 project and he did not go into much detail about differences between single ended and balanced.
Can anyone state what the audible difference would be?
I will eventually get one of these and run it more normally than I did my first board! Will use regular supplies and dispense with the batteries. I think the batteries are superior but I do not want the hassle for what I suspect would now be a negligible difference.
I am curious about trying out the balanced configuration. But I have not read much user comments about this other than jjanssen's 1541 project and he did not go into much detail about differences between single ended and balanced.
Can anyone state what the audible difference would be?
Hello Rick, there are advantages of symmetric signal processing, but also disadvantage.
Advantages are the won 3dB, the double slew rate, the increased disturbance, the waiver of the mass during processing ...
Disadvantages are the significantly higher component costs, everything twice, the required accuracy of the lines ...
With a DAC of Soekris Quallity, without internal volume control, most of the benefits play a smaller role.
In the endfekt then decides the rest of the system which is "better", your amplifier favors symmetric signals should you offer him this, if not you will be just as happy with the asymmetrical version.
Greetings JJ
@soekris
When measuring the DAM at the raw outputs I see in the spectrogram a (very) low level peak who's frequency wanders in a period of about 2 minutes in the range somewhere between 100Hz and 150Hz.
The peak only wanders if there is a "signal" (that is if there is an I2S input), otherwise it remains fixed.
The wandering is damped (third picture)
It seams to be independent of the played signal (third picture, playing silence as well as 1kHz).
The wandering amplitude gets less with higher sampling frequencies (second picture).
I first took it for an flaw of the ADC, but have now seen it again with an other ADC and only with the DAM connected.
Have you any idea what this could be ... some artifact of the fifo reclocking mechanism?? Not that it is, at this level, of any importance for the sound ... just curiosity.
The ADC sample rate is 192kHz, 0dB correspond to an input of 3,16VRMS.
The FFT is of length 2^17 with van Hann window.
The DAM is a 1021 rev1 connected with USB via an Amanero.
First picture (from bottom to top) player stopped, a 1kHz signal with fs=48kHz is played for about 2 minutes (recognizable at the white beam to the right), player stopped.
Second picture (from bottom to top) with pauses where player is stopped, a 1kHz signal with fs=48kHz , fs=96kHz fs=192kHz is played.
Third picture (from bottom to top) player stopped, silence is played, a 1kHz signal is played for a longer period, silence is played, player is stopped for an instant and silence is played.
When measuring the DAM at the raw outputs I see in the spectrogram a (very) low level peak who's frequency wanders in a period of about 2 minutes in the range somewhere between 100Hz and 150Hz.
The peak only wanders if there is a "signal" (that is if there is an I2S input), otherwise it remains fixed.
The wandering is damped (third picture)
It seams to be independent of the played signal (third picture, playing silence as well as 1kHz).
The wandering amplitude gets less with higher sampling frequencies (second picture).
I first took it for an flaw of the ADC, but have now seen it again with an other ADC and only with the DAM connected.
Have you any idea what this could be ... some artifact of the fifo reclocking mechanism?? Not that it is, at this level, of any importance for the sound ... just curiosity.
The ADC sample rate is 192kHz, 0dB correspond to an input of 3,16VRMS.
The FFT is of length 2^17 with van Hann window.
The DAM is a 1021 rev1 connected with USB via an Amanero.
First picture (from bottom to top) player stopped, a 1kHz signal with fs=48kHz is played for about 2 minutes (recognizable at the white beam to the right), player stopped.
Second picture (from bottom to top) with pauses where player is stopped, a 1kHz signal with fs=48kHz , fs=96kHz fs=192kHz is played.
Third picture (from bottom to top) player stopped, silence is played, a 1kHz signal is played for a longer period, silence is played, player is stopped for an instant and silence is played.
Clock tracking? You described the algorithm as using a high/low watermark when you adjust the clock. Shouldn't we see steps rather than a soft sinus pattern?
//
//
If you are willing to describe your clock handling I think many of us are interested.
I asked you if you had a watermark in the buffer, and when it was filled or emptied to the level of this mark, you adjusted the clock frequency. This is of course som sort of tracking but I assume this should mean stepwise tracking (changing of clock) and not a continuous sinus shaped change as the measurement somehow indicate.
Well, still, how could this create a tone? And why at 120 Hz? Strange...
Why I'm at this is that people report impact on different clocks etc. There should not be any if your elegant solution works well.
And yet an the other hans, people hear, and measure 🙂 , a lot of strange things that may or may not exist 🙂
//
I asked you if you had a watermark in the buffer, and when it was filled or emptied to the level of this mark, you adjusted the clock frequency. This is of course som sort of tracking but I assume this should mean stepwise tracking (changing of clock) and not a continuous sinus shaped change as the measurement somehow indicate.
Well, still, how could this create a tone? And why at 120 Hz? Strange...
Why I'm at this is that people report impact on different clocks etc. There should not be any if your elegant solution works well.
And yet an the other hans, people hear, and measure 🙂 , a lot of strange things that may or may not exist 🙂
//
If you order the clock to change, does it do a gradual change or a step to the new frequency?
//
//
Thanks, jjansen, your counsel is appreciated.
That sickness of always wanting more ...
The only balanced amplifiers in my system are the lowest bass ones. Don't think that should guide my actions.
I really like SOEKRIS and am glad you reinvigorated my interest in putting together a digital system again. Not that I will be following your computer scheme though it sounds intriguing. I just do not like USB.
Now to start collecting parts again.
Please keep us apprised of your trials and tribulations, along with successes.
Take care,
That sickness of always wanting more ...
The only balanced amplifiers in my system are the lowest bass ones. Don't think that should guide my actions.
I really like SOEKRIS and am glad you reinvigorated my interest in putting together a digital system again. Not that I will be following your computer scheme though it sounds intriguing. I just do not like USB.
Now to start collecting parts again.
Please keep us apprised of your trials and tribulations, along with successes.
Take care,
I was more asking about the behaviour of the clock component on the board... if you order a 10 Hz increase - how will the 6 leg component execute that? Gradually or in a brute step?
The rate of change of that tone seem to be: 40Hz in 49 seconds i.e. 0,8 Hz/s. Thats much times higher than the PLL bandwidth so it should be absorbed - right?
With a PLL BW of 0,1 Hz we should not see clock adjust orders more often than every 10 seconds - right?
Agree - it's at a really low level 🙂 but still interesting.
A command to list the last 10 clock change orders incl. relative time stamp and new frequency 😉 ? This could be beneficial for you as it would reveal bad I2S/spdif lines/source clocks...
//
The rate of change of that tone seem to be: 40Hz in 49 seconds i.e. 0,8 Hz/s. Thats much times higher than the PLL bandwidth so it should be absorbed - right?
With a PLL BW of 0,1 Hz we should not see clock adjust orders more often than every 10 seconds - right?
Agree - it's at a really low level 🙂 but still interesting.
A command to list the last 10 clock change orders incl. relative time stamp and new frequency 😉 ? This could be beneficial for you as it would reveal bad I2S/spdif lines/source clocks...
//
Looking at the 1321 circuit board I see neither TP1 nor TP2.
Please, can you shed some light on this?
Thanks
Matt